Works about VERY large scale circuit integration

Results: 884

A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER.

Published in:

International Journal of Nanoscience, 2013, v. 12, n. 2, p. -1, doi. 10.1142/S0219581X13500117

By:

SHRIVAS, JAYRAM;
AKASHE, SHYAM;
TIWARI, NITESH

Publication type:

Article

VLSI implementation of an energy-efficient color image compressor using improved block truncation coding and enhanced Golomb-rice coding for wireless sensor networks.

Published in:

Journal of Supercomputing, 2024, v. 80, n. 17, p. 24807, doi. 10.1007/s11227-024-06311-6

By:

Nirmala, R.;
Begum, S. Ariffa;
Selvanayagi, A.;
Ramya, P.

Publication type:

Article

A mini I<sup>2</sup>C bus interface circuit design and its VLSI implementation.

Published in:

Journal of Supercomputing, 2024, v. 80, n. 16, p. 23794, doi. 10.1007/s11227-024-06370-9

By:

Huang, Caixia;
Yang, Sen

Publication type:

Article

Low-Temperature Coating of Si Oxide by Aerosol Assisted CVD.

Published in:

Microscopy & Microanalysis, 2024, v. 30, p. 1, doi. 10.1093/mam/ozae044.286

By:

Salazar-García, L;
Pizá-Ruíz, P;
Garay-Reyes, C G;
Estrada-Guel, I;
Martínez-Sánchez, R

Publication type:

Article

FPGA‐based implementation of floating point processing element for the design of efficient FIR filters.

Published in:

IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 296, doi. 10.1049/cdt2.12010

By:

John, Tintu Mary;
Chacko, Shanty

Publication type:

Article

超大规模集成电路布图规划方法研究综述.

Published in:

Journal of Jilin University (Science Edition) / Jilin Daxue Xuebao (Lixue Ban), 2025, v. 63, n. 1, p. 139, doi. 10.13413/j.cnki.jdxblxb.2024495

By:

史梓慧;
欧阳丹彤;
张立明

Publication type:

Article

BLACK BOX MODEL-BASED SELF HEALING SOLUTION FOR STUCK-AT-FAULTS IN COMBINATIONAL CIRCUITS.

Published in:

International Review of Applied Sciences & Engineering, 2017, v. 8, n. 2, p. 117, doi. 10.1556/1848.2017.8.2.3

By:

MEYYAPPAN, S.;
ALAMELUMANGAI, V.

Publication type:

Article

A discrete dynamic convexized method for VLSI circuit partitioning.

Published in:

Optimization Methods & Software, 2013, v. 28, n. 4, p. 670, doi. 10.1080/10556788.2012.663372

By:

Chen, Jiarui;
Zhu, Wenxing

Publication type:

Article

Time-to-Digital Converter-Based Maximum Delay Sensor for On-Line Timing Error Detection in Logic Block of Very Large Scale Integration Circuits.

Published in:

Sensors & Materials, 2015, v. 27, n. 10, p. 933

By:

Kentaroh Katoh;
Kazuteru Namba

Publication type:

Article

Missing/Extra Via Check Algorithm for Advanced VLSI Analog Designs.

Published in:

Electronics (2079-9292), 2025, v. 14, n. 3, p. 635, doi. 10.3390/electronics14030635

By:

Grochowska, Marika;
Pleskacz, Witold A.

Publication type:

Article

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 21, p. 4471, doi. 10.3390/electronics12214471

By:

Chiper, Doru Florin;
Cracan, Arcadie

Publication type:

Article

Accelerating DC Circuit Simulation through Feature Selection and LSTM-Based Time-Step Control.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 8, p. 1927, doi. 10.3390/electronics12081927

By:

Jin, Zhou;
Yang, Ziyi;
Pei, Haojie;
Zha, Xiaru;
Bai, Yinuo;
Niu, Dan;
Zhou, Zhenya;
Wu, Xiao

Publication type:

Article

Extraction of Interconnect Parasitic Capacitance Matrix Based on Deep Neural Network.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 6, p. 1440, doi. 10.3390/electronics12061440

By:

Ma, Yaoyao;
Xu, Xiaoyu;
Yan, Shuai;
Zhou, Yaxing;
Zheng, Tianyu;
Ren, Zhuoxiang;
Chen, Lan

Publication type:

Article

High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 5, p. 1210, doi. 10.3390/electronics12051210

By:

Wu, Yujun;
Wu, Bin;
Zhou, Xiaoping

Publication type:

Article

Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 3, p. 739, doi. 10.3390/electronics12030739

By:

Chiou, Yih-Shyh;
Chen, Shih-Lun;
Chen, Wei-Ting

Publication type:

Article

Progress of Placement Optimization for Accelerating VLSI Physical Design.

Published in:

Electronics (2079-9292), 2023, v. 12, n. 2, p. 337, doi. 10.3390/electronics12020337

By:

Qiu, Yihang;
Xing, Yan;
Zheng, Xin;
Gao, Peng;
Cai, Shuting;
Xiong, Xiaoming

Publication type:

Article

A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 22, p. 3704, doi. 10.3390/electronics11223704

By:

Zulberti, Luca;
Di Matteo, Stefano;
Nannipieri, Pietro;
Saponara, Sergio;
Fanucci, Luca

Publication type:

Article

Specially-Designed Out-of-Order Processor Architecture for Microcontrollers.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 19, p. 2989, doi. 10.3390/electronics11192989

By:

Hu, Yunhao;
Chen, Jie;
Zhu, Kaiben;
Xing, Qijun;
Liu, Wei;
Shen, Junfeng;
Gao, Ge

Publication type:

Article

Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 18, p. N.PAG, doi. 10.3390/electronics11182965

By:

Pudi, Dhilleswararao;
Harrison, Samuel Jigme;
Stathis, Dimitrios;
Boppu, Srinivas;
Hemani, Ahmed;
Cenkeramaddi, Linga Reddy

Publication type:

Article

Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 15, p. 2461, doi. 10.3390/electronics11152461

By:

Mendez, Tanya;
Nayak, Subramanya G.;
Kumar P., Vasanth;
S. R., Vijay;
Kedlaya K., Vishnumurthy

Publication type:

Article

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 15, p. 2416, doi. 10.3390/electronics11152416

By:

Chiper, Doru Florin;
Cracan, Arcadie;
Andries, Vasilica-Daniela

Publication type:

Article

Template-Based Semi-Formal Approach to Robust Equivalence Checking.

Published in:

Electronics (2079-9292), 2022, v. 11, n. 11, p. 1691, doi. 10.3390/electronics11111691

By:

Wang, Qinhao;
Fujita, Masahiro

Publication type:

Article

Congestion Prediction in FPGA Using Regression Based Learning Methods.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 16, p. 1995, doi. 10.3390/electronics10161995

By:

Goswami, Pingakshya;
Bhatia, Dinesh

Publication type:

Article

VLSI Architectures of a Wiener Filter for Video Coding.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 16, p. 1961, doi. 10.3390/electronics10161961

By:

Walid, Walid;
Armanno, Giorgio;
Di Paola, Sandro;
Ruo Roch, Massimo;
Masera, Guido;
Martina, Maurizio

Publication type:

Article

Best Practices for the Deployment of Edge Inference: The Conclusions to Start Designing.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 16, p. 1912, doi. 10.3390/electronics10161912

By:

Flamis, Georgios;
Kalapothas, Stavros;
Kitsos, Paris

Publication type:

Article

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 14, p. 1656, doi. 10.3390/electronics10141656

By:

Chiper, Doru Florin;
Cotorobai, Laura-Teodora

Publication type:

Article

High Precision Multiplier for RNS {2 n −1,2 n ,2 n +1}.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 9, p. 1113, doi. 10.3390/electronics10091113

By:

Ma, Shang;
Hu, Shuai;
Yang, Zeguo;
Wang, Xuesi;
Liu, Meiqing;
Hu, Jianhao;
Khateb, Fabian

Publication type:

Article

Improving Model Capacity of Quantized Networks with Conditional Computation.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 8, p. 886, doi. 10.3390/electronics10080886

By:

Pham, Phuoc;
Chung, Jaeyong

Publication type:

Article

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 7, p. 862, doi. 10.3390/electronics10070862

By:

Chung, Rih-Lung;
Chen, Chen-Wei;
Chen, Chiung-An;
Abu, Patricia Angela R.;
Chen, Shih-Lun;
Granado, Otoniel Mario López

Publication type:

Article

Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 3, p. 230, doi. 10.3390/electronics10030230

By:

Cho, Jaechan;
Jung, Yongchul;
Lee, Seongjoo;
Jung, Yunho;
Masera, Guido

Publication type:

Article

Low-Complexity Address Generation for Multiuser Detectors in IDMA Systems.

Published in:

Electronics (2079-9292), 2020, v. 9, n. 12, p. 2069, doi. 10.3390/electronics9122069

By:

Kong, Byeong Yong

Publication type:

Article

Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems.

Published in:

Electronics (2079-9292), 2020, v. 9, n. 10, p. 1657, doi. 10.3390/electronics9101657

By:

Sun, Lu;
Wu, Bin;
Ye, Tianchun

Publication type:

Article

ABCD parameter based analytical AC modeling of novel Cu–carbon hybrid interconnects for noise constrained nanoscale systems.

Published in:

Scientific Reports, 2025, v. 15, n. 1, p. 1, doi. 10.1038/s41598-024-81729-9

By:

Kumari, Bhawana;
Sahoo, Manodipan;
Sharma, Rohit

Publication type:

Article

DESIGN AND VALIDATION OF LOW POWER, HIGH PERFORMANCE PARALLEL PREFIX ADDERS.

Published in:

i-Manager's Journal on Electronics Engineering, 2025, v. 15, n. 3, p. 48, doi. 10.26634/jele.15.3.21813

By:

PARASA, SIVADURGARAO;
VENKATA TEJASWINI, PARUCHURI NAGA;
HUZAIFA, MOHAMMAD;
VARDHINI, VAGU;
GEETHIKA, PAKALAPATI;
RAMA SHANMUKH SAI, SEGU TARAKA

Publication type:

Article

DESIGN OF DUTY CYCLE CORRECTION CIRCUIT USING ASIC IMPLEMENTATION FOR HIGH SPEED COMMUNICATION.

Published in:

i-Manager's Journal on Electronics Engineering, 2023, v. 13, n. 3, p. 33

By:

K. B., SIDDESH;
S., ROOPA;
B. A., FARZANA PARVEEN;
T., TANUJA

Publication type:

Article

DESIGN OF HYBRID FULL ADDERS FOR POWER MINIMIZATION AND HIGH SPEED USING XOR AND XNOR GATES.

Published in:

i-Manager's Journal on Electronics Engineering, 2019, v. 10, n. 1, p. 22, doi. 10.26634/jele.10.1.16227

By:

AYLAPOGU, PRAMOD KUMAR

Publication type:

Article

DESIGN OF HIGH PERFORMANCE PULSE GENERATOR TO PERFORM AUTOMATIC TEST IN VLSI CIRCUITS.

Published in:

i-Manager's Journal on Electronics Engineering, 2019, v. 9, n. 3, p. 26, doi. 10.26634/jele.9.3.15953

By:

LOKESH, P.;
THRIMURTHULU, V.;
PRIYA, L. MIHIRA

Publication type:

Article

COMPARISON OF DIFFERENT DESIGNS OF PULSE TRIGGERED FLIP-FLOP BASED SHIFT REGISTER AT 32nm TECHNOLOGY.

Published in:

i-Manager's Journal on Electronics Engineering, 2017, v. 7, n. 4, p. 28, doi. 10.26634/jele.7.4.13686

By:

KUMAR, SANDEEP;
DESHMUKH, KHEMRAJ

Publication type:

Article

DESIGN OF REVERSIBLE ARITHMETIC AND LOGIC UNIT.

Published in:

i-Manager's Journal on Electronics Engineering, 2017, v. 7, n. 3, p. 17, doi. 10.26634/jele.7.3.13560

By:

SAHU, AJAY KUMAR;
KAMARGAONKAR, CHANDRASHEKHAR

Publication type:

Article

VOLTAGE MODE UNIVERSAL FIRST ORDER FILTER EMPLOYING SINGLE OTRA.

Published in:

i-Manager's Journal on Electronics Engineering, 2015, v. 5, n. 4, p. 24, doi. 10.26634/jele.5.4.3542

By:

GAHLAWAT, HONEY;
KUMAR, HEMANT;
KAMNANI, JATIN;
DAGAR, GAURAV;
PANDEY, RAJESHWARI

Publication type:

Article

VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS.

Published in:

i-Manager's Journal on Electronics Engineering, 2014, v. 5, n. 1, p. 27, doi. 10.26634/jele.5.1.3320

By:

ANUSHA, JEEVA;
THRIMURTHULU, V.

Publication type:

Article

REPEATER SIZING FOR CROSS-TALK MITIGATION IN COUPLED VLSI INTERCONNECTS.

Published in:

i-Manager's Journal on Electronics Engineering, 2013, v. 3, n. 3, p. 6, doi. 10.26634/jele.3.3.2252

By:

KHANNA, GARGI;
CHANDEL, RAJEEVAN;
CHANDEL, ASHWANI

Publication type:

Article

Impact of Device Sizing on Electrical Properties of DG-SOI-MOSFET Using Octave Software.

Published in:

Journal of Nano- & Electronic Physics, 2022, v. 14, n. 5, p. 1, doi. 10.21272/jnep.14(5).05025

By:

Djerioui, M.;
Hebali, M.;
Abboun Abid, M.

Publication type:

Article

Energy Efficient Design of Four-operand Multiplier Architecture using CNTFET Technology.

Published in:

Journal of Nano- & Electronic Physics, 2018, v. 10, n. 2, p. 1, doi. 10.21272/jnep.10(2).02022

By:

Charmchi, N.;
Reshadinezhad, M. R.

Publication type:

Article

The class Steiner minimal tree problem: a lower bound and test problem generation.

Published in:

Acta Informatica, 2000, v. 37, n. 3, p. 193, doi. 10.1007/s002360000042

By:

Yang, Boting;
Gillard, Paul

Publication type:

Article

Design and Implementation of Crosstalk Avoidance Using Bit-Stuffing Algorithms in VLSI Circuits.

Published in:

IUP Journal of Telecommunications, 2018, v. 10, n. 1, p. 33

By:

Jyothi, B.;
Obulesu, B.

Publication type:

Article

Effective lattice structures for separable two-dimensional orthogonal wavelet transforms.

Published in:

Bulletin of the Polish Academy of Sciences: Technical Sciences, 2022, v. 70, n. 3, p. 1, doi. 10.24425/bpasts.2022.141005

By:

PUCHALA, Dariusz

Publication type:

Article

An Analog VLSI Architecture for High Speed, Low Power Object Tracking.

Published in:

International Journal of Distributed Sensor Networks, 2009, v. 5, n. 6, p. 675, doi. 10.1080/15501320802581557

By:

Habibi, Mehdi;
Sayedi, Masoud

Publication type:

Article

An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits.

Published in:

International Journal of Distributed Sensor Networks, 2008, v. 4, n. 2, p. 213, doi. 10.1080/15501320802001259

By:

Srivastava, Ashok;
Zhang, Chuang

Publication type:

Article

A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application.

Published in:

Journal of Nanotechnology, 2018, p. 1, doi. 10.1155/2018/2934268

By:

Singar, Sumitra;
Joshi, N. K.;
Ghosh, P. K.

Publication type:

Article