Vedic mathematics training in specific learning difficulty: A study on upper primary children.
- Published in:
- Indian Journal of Positive Psychology, 2018, v. 9, n. 1, p. 97, doi. 10.15614/ijpp.v9i01.11750
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- Publication type:
- Article
Works matching Vedic mathematics
Results: 62
1
2
DESIGN AND ANALYSIS OF 32X32 BIT ALU USING HIGH-SPEED VEDIC-WALLACE MULTIPLIER BASED ON VEDIC MATHEMATICS.
- Published in:
- i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 3, p. 7, doi. 10.26634/jele.6.3.5954
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- Article
3
INTRODUCTION TO VEDIC MATHEMATICS.
- Published in:
- Journal of Applied Global Research, 2012, v. 5, n. 14, p. 1
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- Article
4
DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS.
- Published in:
- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 7, p. -1, doi. 10.1142/S0218126614500923
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- Publication type:
- Article
5
VEDIC MATHEMATICS.
- Published in:
- Human: Journal for Interdisciplinary Studies, 2015, v. 5, n. 2, p. 23, doi. 10.21554/hrr.091509
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- Publication type:
- Article
6
ECC for Heterogeneous Wireless Sensor Networks Using Ancient Indian Vedic Mathematics.
- Published in:
- ITEA Journal of Test & Evaluation, 2015, v. 36, n. 3, p. 231
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- Publication type:
- Article
7
Aesthetic appeal and utility of Vedic mathematics: An introduction.
- Published in:
- Aisthesis: Pratiche, Linguaggi e Saperi dell'Estetico, 2023, v. 16, n. 1, p. 181, doi. 10.36253/Aisthesis-14287
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- Publication type:
- Article
8
Performance Evaluation of Squaring Operation by Vedic Mathematics.
- Published in:
- IETE Journal of Research, 2011, v. 57, n. 1, p. 39, doi. 10.4103/0377-2063.78327
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- Article
9
Implementation of 2D Discrete Cosine Transform Using Vedic Mathematic Algorithm.
- Published in:
- IUP Journal of Telecommunications, 2016, v. 8, n. 2, p. 77
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- Article
10
Investigation of Yoga Pranayama and Vedic Mathematics on Mindfulness, Aggression and Emotion Regulation.
- Published in:
- International Journal of Yoga, 2017, v. 10, n. 3, p. 138, doi. 10.4103/0973-6131.213470
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- Article
11
Vedic Mathematics mattu Vedagalalli Vidnyana.
- Published in:
- 2017
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- Publication type:
- Book Review
12
A DESIGN AND IMPLEMENTATION OF HIGH SPEED IEEE-754 DOUBLE PRECISION FLOATING POINT UNIT BASED ON VEDIC TECHNIQUES.
- Published in:
- i-Manager's Journal on Electronics Engineering, 2017, v. 8, n. 1, p. 19, doi. 10.26634/jele.8.1.13836
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- Publication type:
- Article
13
Impact of pranayama and vedic mathematics on math anxiety and cognitive skills.
- Published in:
- Yoga Mimamsa, 2017, v. 49, n. 2, p. 53, doi. 10.4103/ym.ym_13_17
- Publication type:
- Article
14
Squaring Circuit Using 14nmFinFET Technology with Vedic Mathematics Approach.
- Published in:
- IETE Journal of Research, 2024, v. 70, n. 10, p. 7980, doi. 10.1080/03772063.2024.2355662
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- Publication type:
- Article
15
An Approach to Implement Vedic Mathematics to Agricultural System: A Review.
- Published in:
- Agricultural Reviews, 2023, v. 44, n. 1, p. 89, doi. 10.18805/ag.R-2320
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- Publication type:
- Article
16
Design of 16 Bit Vedic Multiplier Using Semi-Custom and Full Custom Approach.
- Published in:
- Journal of Engineering Science & Technology Review, 2017, v. 10, n. 2, p. 220
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- Article
17
Ghosts of mathematicians past: Bharati Krishna and Gabriel Cramer.
- Published in:
- Australian Senior Mathematics Journal, 2017, v. 31, n. 1, p. 48
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- Publication type:
- Article
18
Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA.
- Published in:
- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 3, p. 1205, doi. 10.11591/ijece.v6i3.9457
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- Publication type:
- Article
19
Design of Multiplier for Medical Image Compression Using Urdhava Tiryakbhyam Sutra.
- Published in:
- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 3, p. 1140, doi. 10.11591/ijece.v6i3.9031
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- Publication type:
- Article
20
Vedic Mathematics: A Mathematical Tale from the Ancient Veda to Modern Times: by Giuseppe Dattoli, Silvia Licciardi, and Marcello Artioli, World Scientific, 2021, 232 pp., $68 (HB), ISBN 9789811221552.
- Published in:
- Technometrics, 2023, v. 65, n. 1, p. 131, doi. 10.1080/00401706.2022.2163833
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- Publication type:
- Article
21
Realization of 2-bit multiplier based on Vedic mathematics using electro-absorption microring modulator.
- Published in:
- Optical Engineering, 2024, v. 63, n. 10, p. 105104, doi. 10.1117/1.OE.63.10.105104
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- Publication type:
- Article
22
Design of High Performance IIR Filter Using Vedic Multiplication Method.
- Published in:
- Technical Journal of University of Engineering & Technology Taxila, 2016, v. 21, n. 4, p. 50
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- Article
23
Design of Vedic Architecture for High Speed DCT.
- Published in:
- International Review on Computers & Software, 2014, v. 9, n. 2, p. 330
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- Article
24
Vedic Algorithms Revisited By Mathematics Teachers And Computer Science Teachers: A Comparative Study.
- Published in:
- International Journal for Technology in Mathematics Education, 2005, v. 12, n. 2, p. 73
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- Publication type:
- Article
25
From Altars to Algorithms: The Enduring Legacy of Vedic Mathematics for Holistic Education.
- Published in:
- Holistic Education Review, 2024, v. 4, n. 2, p. 1
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- Publication type:
- Article
26
Vedic Mathematics and Science in Vedas.
- Published in:
- Current Science (00113891), 2020, v. 118, n. 7, p. 1129
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- Publication type:
- Article
27
Antichi modi per eseguire le moltiplicazioni.
- Published in:
- Atti della Società dei Naturalisti e Matematici di Modena, 2022, v. 153, p. 345
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- Article
28
Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra.
- Published in:
- Sādhanā: Academy Proceedings in Engineering Sciences, 2019, v. 44, n. 9, p. N.PAG, doi. 10.1007/s12046-019-1180-3
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- Publication type:
- Article
29
Square & Cube Computation using Vedic Algorithms in FPGA.
- Published in:
- International Journal of Nanoelectronics & Materials, 2020, v. 13, n. 2, p. 315
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- Publication type:
- Article
30
High Speed Vedic Multiplier for Digital Signal Processors.
- Published in:
- IETE Journal of Research, 2009, v. 55, n. 6, p. 282, doi. 10.4103/0377-2063.59167
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- Publication type:
- Article
31
Efficient ASIC and FPGA implementation of cube architecture.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2017, v. 11, n. 1, p. 43, doi. 10.1049/iet-cdt.2016.0043
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- Publication type:
- Article
32
Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata.
- Published in:
- Electronics (2079-9292), 2020, v. 9, n. 6, p. 1036, doi. 10.3390/electronics9061036
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- Publication type:
- Article
33
McCMOS Based Low Power and High Speed 32 x 32 Bit Nikhilum Multiplier.
- Published in:
- Reliability: Theory & Applications, 2020, v. 15, n. 2, p. 72
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- Article
34
Gate diffusion input based 4‐bit Vedic multiplier design.
- Published in:
- IET Circuits, Devices & Systems (Wiley-Blackwell), 2018, v. 12, n. 6, p. 764, doi. 10.1049/iet-cds.2017.0454
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- Publication type:
- Article
35
Implementation of Efficient Vedic Multiplier and Its Performance Evaluation.
- Published in:
- Journal of Circuits, Systems & Computers, 2023, v. 32, n. 15, p. 1, doi. 10.1142/S0218126623502535
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- Publication type:
- Article
36
Performance Analysis of 4 bit Vedic Multiplier for Low Power Computing.
- Published in:
- Journal of Active & Passive Electronic Devices, 2022, v. 16, n. 4, p. 283
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- Publication type:
- Article
37
Area, power efficient Vedic multiplier architecture using novel 4:2 compressor.
- Published in:
- Sādhanā: Academy Proceedings in Engineering Sciences, 2023, v. 48, n. 4, p. 1, doi. 10.1007/s12046-023-02274-1
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- Publication type:
- Article
38
A Novel and Efficient Left-to-Right Binary Adder Architecture for reduced Area and Power Metrics in VLSI Design.
- Published in:
- Engineering, Technology & Applied Science Research, 2025, v. 15, n. 3, p. 22629, doi. 10.48084/etasr.9840
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- Publication type:
- Article
39
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA.
- Published in:
- Circuits, Systems & Signal Processing, 2017, v. 36, n. 3, p. 998, doi. 10.1007/s00034-016-0335-2
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- Publication type:
- Article
40
FPGA realization of an efficient image scalar with modified area generation technique.
- Published in:
- Multimedia Tools & Applications, 2019, v. 78, n. 16, p. 23707, doi. 10.1007/s11042-019-7592-6
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- Publication type:
- Article
41
An FPGA and ASIC Implementation of Cubing Architecture.
- Published in:
- Wireless Personal Communications, 2022, v. 125, n. 4, p. 3379, doi. 10.1007/s11277-022-09715-w
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- Publication type:
- Article
42
REFORM OF TEACHING A TRIGONOMETRY COURSE.
- Published in:
- Georgia Journal of Science, 2015, v. 73, n. 2-4, p. 136
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- Publication type:
- Article
43
Comparative analysis of Yavadunam Tavadunikrtya Varganca Yojayet Vedic multiplier for embedded DNN.
- Published in:
- Sādhanā: Academy Proceedings in Engineering Sciences, 2022, v. 47, n. 2, p. 1, doi. 10.1007/s12046-022-01843-0
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- Publication type:
- Article
44
Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications.
- Published in:
- Sādhanā: Academy Proceedings in Engineering Sciences, 2020, v. 45, n. 1, p. 1, doi. 10.1007/s12046-020-01500-4
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- Publication type:
- Article
45
VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier.
- Published in:
- Journal of Circuits, Systems & Computers, 2018, v. 27, n. 5, p. -1, doi. 10.1142/S0218126618500779
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- Publication type:
- Article
46
Design of Vedic Multiplier via Modified Gate Diffusion Technique for Applications in Digital Signal Processor.
- Published in:
- Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 3/4, p. 251
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- Publication type:
- Article
47
Design and synthesis of reversible Vedic multiplier using cadence 180 nm technology for low-power high-speed applications.
- Published in:
- Scientific Reports, 2025, v. 15, n. 1, p. 1, doi. 10.1038/s41598-025-04002-7
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- Publication type:
- Article
48
Design and synthesis of reversible Vedic multiplier using cadence 180 nm technology for low-power high-speed applications.
- Published in:
- Scientific Reports, 2025, v. 15, n. 1, p. 1, doi. 10.1038/s41598-025-04002-7
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- Publication type:
- Article
49
A novel nano‐scale architecture of Vedic multiplier using majority logic in quantum‐dot cellular automata technology.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2022, v. 58, n. 17, p. 660, doi. 10.1049/ell2.12552
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- Publication type:
- Article
50
Indian Mathematics.
- Published in:
- Mathematical Intelligencer, 2000, v. 22, n. 4, p. 80, doi. 10.1007/BF03026776
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- Publication type:
- Article