Works matching VHDL (Computer hardware description language)

Results: 122

Ties that bind [hardware description languages].

Published in:

Electronics Systems & Software, 2006, v. 4, n. 5, p. 8, doi. 10.1049/ess:20060501

By:

Crone, A.

Publication type:

Article

A new face for FPGA design.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 28, doi. 10.1049/ess:20060305

By:

Edwards, C.

Publication type:

Article

Tune analogue simulations for accuracy and speed.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 16, doi. 10.1049/ess:20060302

By:

Raynaud, P.;
Oudinot, J.

Publication type:

Article

Blueprint for logic.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 42, doi. 10.1049/ess:20060308

By:

Sordoillet, J.;
Davey, S.

Publication type:

Article

Contribution to Synchronization and Tracking Modelisation in a CDMA Receiver.

Published in:

Journal of Engineering (2314-4912), 2013, p. 1, doi. 10.1155/2013/936495

By:

Hassani, Aicha Alami;
Zouak, Mohcine;
Mrabti, Mostafa

Publication type:

Article

Synthesizing VHDL from Activity Models in UML 2.

Published in:

International Journal of Circuit Theory & Applications, 2014, v. 42, n. 5, p. 542, doi. 10.1002/cta.1874

By:

Balderas‐Contreras, Tomás;
Cumplido, René;
Rodríguez, Gustavo

Publication type:

Article

Synthesis and implementation of the ordered access memory in programmable logic devices.

Published in:

Metallurgical & Mining Industry, 2016, n. 4, p. 58

By:

Lishchyna, Nataliia;
Lishchyna, Valerii;
Herasymchuk, Oleh;
Yashchuk, Andrii

Publication type:

Article

DESIGN AND IMPLEMENTATION OF GA-BASED FUZZY SYSTEM ON FPGA CHIP.

Published in:

Cybernetics & Systems, 2008, v. 39, n. 1, p. 79, doi. 10.1080/01969720701710220

By:

Ching-Chang Wong;
Yu-Han Lin

Publication type:

Article

Digital control technologies for improving the power quality of power supplies.

Published in:

Neural Computing & Applications, 2013, v. 22, p. 235, doi. 10.1007/s00521-012-1058-3

By:

Shah, P.;
Saxena, Rakesh;
Chawla, M.

Publication type:

Article

Neural network training based on FPGA with floating point number format and it's performance.

Published in:

Neural Computing & Applications, 2011, v. 20, n. 2, p. 195, doi. 10.1007/s00521-010-0423-3

By:

Çavuşlu, Mehmet;
Karakuzu, Cihan;
Şahin, Suhap;
Yakut, Mehmet

Publication type:

Article

Highly Parallel Modular Multiplier for Elliptic Curve Cryptography in Residue Number System.

Published in:

Circuits, Systems & Signal Processing, 2017, v. 36, n. 3, p. 1027, doi. 10.1007/s00034-016-0336-1

By:

Asif, Shahzad;
Kong, Yinan

Publication type:

Article

Microprocessor design using hardware description language.

Published in:

European Journal of Engineering Education, 2008, v. 33, n. 4, p. 425, doi. 10.1080/03043790802253384

By:

Mita, Rosario;
Palumbo, Gaetano

Publication type:

Article

Relating Event and Trace Semantics of Hardware Description Languages.

Published in:

Computer Journal, 2002, v. 45, n. 1, p. 27, doi. 10.1093/comjnl/45.1.27

By:

Gordon, Michael J. C.

Publication type:

Article

Image Encryption using Simple Algorithm on FPGA.

Published in:

Telkomnika, 2015, v. 13, n. 4, p. 1153, doi. 10.12928/TELKOMNIKA.v13i4.1787

By:

Prasetio, Barlian Henryranu;
Setiawan, Eko;
Muttaqin, Adharul

Publication type:

Article

FPGA Implementation ofLow-Area Square Root Calculator.

Published in:

Telkomnika, 2015, v. 13, n. 4, p. 1145, doi. 10.12928/TELKOMNIKA.v13i4.1894

By:

Jidin, Aiman Zakwan;
Sutikno, Tole

Publication type:

Article

Overview on Strategies and Approaches for FPGA Programming.

Published in:

Telkomnika, 2014, v. 12, n. 2, p. 273, doi. 10.12928/TELKOMNIKA.v12i2.1948

By:

Tole Sutikno;
Nik Idris, Nik Rumzi;
Jidin, Aiman Zakwan

Publication type:

Article

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules.

Published in:

Computers, Materials & Continua, 2022, v. 71, n. 3, p. 4319, doi. 10.32604/cmc.2022.022988

By:

Alanazi, Turki M.;
Atitallah, Ahmed Ben

Publication type:

Article

VHDL DESIGN FOR A SPEED LIMIT SIGN SEGMENTATION ALGORITHM.

Published in:

IADIS International Journal on Computer Science & Information Systems, 2017, v. 12, n. 2, p. 32

By:

Rouabeh, Hanene;
Abdelmoula, Chokri;
Masmoudi, Mohamed

Publication type:

Article

Performance Evaluation of Squaring Operation by Vedic Mathematics.

Published in:

IETE Journal of Research, 2011, v. 57, n. 1, p. 39, doi. 10.4103/0377-2063.78327

By:

Kasliwal, Prabha S.;
Patil, B. P.;
Gautam, D. K.

Publication type:

Article

High Performance Fuzzy Systems for Real World Problems.

Published in:

Advances in Fuzzy Systems, 2012, p. 1, doi. 10.1155/2012/316187

By:

Ross, OscarMontiel;
Cruz, Roberto Sepúlveda;
Castillo, Oscar;
Basturk, Alper

Publication type:

Article

Algorithm & Design of an Efficient Floating Point ADD/SUB Unit for an Experimental CPU.

Published in:

International Journal of Intelligent Information Technology Application, 2009, v. 2, n. 6, p. 273

By:

Joshi, A.;
Lam, S. L.;
Chan, Y. Y.

Publication type:

Article

Analysis for Design and Transformation of Autosynchronous State Machines.

Published in:

Radioengineering, 2010, v. 19, n. 1, p. 99

By:

Kováč, Michal;
Kolouch, Jaromír

Publication type:

Article

Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net.

Published in:

Journal of Integrated Circuits & Systems, 2016, v. 11, n. 2, p. 75, doi. 10.29292/jics.v11i2.432

By:

Silveira, J.;
Cadore, A.;
Barroso, G.;
Marcon, C.;
Webber, T.;
Czekster, R.

Publication type:

Article

DESCRIPCIÓN MODULAR DE UN ESQUEMA DE CODIFICACIÓN CONCATENADO PARA CORRECCIÓN DE ERRORES CON PROGRAMACIÓN DE HARDWARE.

Published in:

INGENIARE - Revista Chilena de Ingeniería, 2008, v. 16, n. 3, p. 310

By:

Ruiz, Cecilia E. Sandoval;
Fedón, Antonio

Publication type:

Article

VHDL Optimized Model of a Multiplier in Finite Fields.

Published in:

Ingeniería y Universidad, 2017, v. 21, n. 2, p. 45, doi. 10.11144/Javeriana.iyu21-2.vhdl

By:

Sandoval-Ruiz, Cecilia

Publication type:

Article

Codificador RS(255,k) en hardware reconfigurable orientado a radio cognitivo.

Published in:

Ingeniería y Universidad, 2013, v. 17, n. 1, p. 77

By:

Sandoval-Ruiz, Cecilia Esperanza;
Fedón-Rovira, Antonio

Publication type:

Article

CODIFICADOR Y DECODIFICADOR DIGITAL REED-SOLOMON PROGRAMADOS PARA HARDWARE RECONFIGURABLE.

Published in:

Ingeniería y Universidad, 2007, v. 11, n. 1, p. 17

By:

Sandoval Ruiz, Cecilia E.;
Fedón, Antonio

Publication type:

Article

Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology.

Published in:

Natural Computing, 2015, v. 14, n. 4, p. 593, doi. 10.1007/s11047-014-9476-z

By:

Kanasugi, Akinori;
Tsukahara, Akihiko;
Ando, Ki

Publication type:

Article

A Synthesizable VHDL Model of the Exact Solution for Three-dimensional Hyperbolic Positioning System.

Published in:

VLSI Design, 2002, v. 15, n. 2, p. 507, doi. 10.1080/1065514021000012129

By:

Bucher, Ralph;
Misra, D.

Publication type:

Article

Design Procedure Based on VHDL Language Transformations.

Published in:

VLSI Design, 2002, v. 14, n. 4, p. 349, doi. 10.1080/10655140290011159

By:

Varga, László;
Hosszú, Gábor;
Kovács, Ferenc

Publication type:

Article

IMAGE CONTOUR SEGMENTATION IN HARDWARE.

Published in:

Radio Electronics, Computer Science, Control, 2015, v. 4, p. 66, doi. 10.15588/1607-3274-2015-4-10

By:

Dimitrios, Amanatidis;
Michael, Dossis;
Iosif, Androulidakis

Publication type:

Article

A Reconfigurable Hybrid Architecture for HomePNA3.1/Ethernet MAC.

Published in:

Majlesi Journal of Electrical Engineering, 2011, v. 5, n. 4, p. 46

By:

Dermany, Mohammad Khalily;
Payegozar, Hamid;
Beheshti, Seyed Ahmad;
Ahmadi, Mohammad

Publication type:

Article

A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs.

Published in:

Journal of Circuits, Systems & Computers, 2019, v. 28, n. 3, p. N.PAG, doi. 10.1142/S0218126619500543

By:

Khalifa, Khaled Ben;
Bedoui, Mohamed Hédi

Publication type:

Article

A Complete Embedded System Design of Breakout Game.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 12, p. -1, doi. 10.1142/S0218126617501882

By:

Tural-Polat, Sadiye Nergis

Publication type:

Article

A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 1, p. 1, doi. 10.1142/S0218126617500153

By:

Koyuncu, İsmail;
Şahin, İbrahim;
Gloster, Clay;
Sarıtekin, Namık Kemal

Publication type:

Article

Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet).

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 3, p. -1, doi. 10.1142/S0218126616400120

By:

Urban, Roberto;
Vierhaus, Heinrich T.;
Schölzel, Mario;
Altmann, Enrico;
Seelig, Horst

Publication type:

Article

Simultaneous Multithreaded Matrix Processor.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 8, p. -1, doi. 10.1142/S0218126615501145

By:

Soliman, Mostafa I.;
Elsayed, Elsayed A.

Publication type:

Article

DESIGN OF A MULTICODE BI-PHASE ENCODER FOR DATA TRANSMISSION.

Published in:

Journal of Circuits, Systems & Computers, 2006, v. 15, n. 1, p. 1, doi. 10.1142/S0218126606002897

By:

AL-ALAWI, RAIDA;
AL-SAMMAK, A. J.

Publication type:

Article

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS.

Published in:

Journal of Circuits, Systems & Computers, 2005, v. 14, n. 2, p. 347, doi. 10.1142/S0218126605002362

By:

Harmanani, Haidar M.;
Saliba, Rony

Publication type:

Article

Actor-Oriented Design of Embedded Hardware and Software Systems.

Published in:

Journal of Circuits, Systems & Computers, 2003, v. 12, n. 3, p. 231, doi. 10.1142/S0218126603000751

By:

Lee, Edward A.;
Neuendorffer, Stephen;
Wirthlin, Michael J.

Publication type:

Article

Induction-Oriented Verification of Replicated Architectures Described in VHDL.

Published in:

Journal of Circuits, Systems & Computers, 2000, v. 10, n. 3/4, p. 181, doi. 10.1142/S0218126600000159

By:

Pierre, Laurence

Publication type:

Article

NSL: A Neuro–Symbolic Language for a Neuro–Symbolic Processor (NSP).

Published in:

International Journal of Neural Systems, 2003, v. 13, n. 2, p. 93, doi. 10.1142/S0129065703001480

By:

Burattini, Ernesto;
de Francesco, Antonio;
de Gregorio, Massimo

Publication type:

Article

Implementation of a Pulse Coupled Neural Network in FPGA.

Published in:

International Journal of Neural Systems, 2000, v. 10, n. 3, p. 171, doi. 10.1142/S0129065700000156

By:

Waldemark, Joakim;
Millberg, Mikael;
Lindblad, Thomas;
Waldemark, Karina;
Becanovic, Vlatko

Publication type:

Article

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

Published in:

PLoS ONE, 2016, v. 11, n. 12, p. 1, doi. 10.1371/journal.pone.0168300

By:

Tlelo-Cuautle, Esteban;
Quintas-Valles, Antonio de Jesus;
de la Fraga, Luis Gerardo;
Rangel-Magdaleno, Jose de Jesus

Publication type:

Article

SEU Fault-Injection in VHDL-Based Processors: A Case Study.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 1, p. 87, doi. 10.1007/s10836-013-5351-6

By:

Mansour, Wassim;
Velazco, Raoul

Publication type:

Article

Review Report on VHDL (VHSIC Hardware description language).

Published in:

International Journal of Recent Research Aspects, 2018, v. 5, n. 1, p. 85

By:

Grewal, Amit

Publication type:

Article

Comparison of Different Design Alternatives for Hardware-in-the-Loop of Power Converters.

Published in:

Electronics (2079-9292), 2021, v. 10, n. 8, p. 926, doi. 10.3390/electronics10080926

By:

Zamiri, Elyas;
Sanchez, Alberto;
Yushkova, Marina;
Martínez-García, Maria Sofia;
de Castro, Angel

Publication type:

Article

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution.

Published in:

Electronics (2079-9292), 2019, v. 8, n. 1, p. 24, doi. 10.3390/electronics8010024

By:

Muñoz-Quijada, Maria;
Sanchez-Barea, Samuel;
Vela-Calderon, Daniel;
Guzman-Miranda, Hipolito

Publication type:

Article

VHDL-AMS-Based Modeling of an Asymmetric H-Type Half-Bridge Converter for Mutually Coupled SRM.

Published in:

Karaelmas Science & Engineering Journal / Karaelmas Fen ve Mühendislik Dergisi, 2018, v. 8, n. 1, p. 211

By:

Şahin, Cihan;
Amaç, Ayşe Ergün;
Karaçor, Mevlüt

Publication type:

Article

Simulating the effects of logic faults in implementation-level VITAL-compliant models.

Published in:

Computing, 2019, v. 101, n. 2, p. 77, doi. 10.1007/s00607-018-0651-4

By:

Tuzov, Ilya;
de Andrés, David;
Ruiz, Juan-Carlos

Publication type:

Article