Works matching IS 25821458 AND DT 2024 AND VI 6 AND IP 2

Results: 15

Performance Evaluation of Mesh, Spidergon, and Mesh of Spidergon (MoS) Topologies in Network-on-Chip (NoC) Architecture.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 130, doi. 10.31838/jvcs/06.02.15

By:

Sravani S.;
Deepak Ch

Publication type:

Article

Thermometer Coding-Based Application-Specific Efficient Mod Adder for Residue Number Systems.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 122, doi. 10.31838/jvcs/06.02.14

By:

Vardhan, K. Vijaya;
Musala, Sarada

Publication type:

Article

VLSI Architecture-Based Implementation of Motion Estimation Algorithm for Underwater Robot Vision System.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 115, doi. 10.31838/jvcs/06.02.13

By:

Tirmare, Aarti Hemant;
Mali, Priyadarshani Shivakumar;
Shirolkar, Amardeep Anandrao;
Shinde, Ganesh Rajaram;
Patil, Vikas Dattatray;
Tirmare, Hemant Appa

Publication type:

Article

Implementation of VLSI Systems Incorporating Advanced Cryptography Model for FPGA-IoT Application.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 107, doi. 10.31838/jvcs/06.02.12

By:

Anandhi, S.;
Rajendrakumar, R.;
Padmapriya, T.;
Manikanthan, S. V.;
Jebanazer, J. Jeneetha;
RajaSekhar, J.

Publication type:

Article

VLSI-Based MED-MEC Architecture for Enhanced IoT Wireless Sensor Networks.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 99, doi. 10.31838/jvcs/06.02.11

By:

Suguna, T.;
Ranjan, Rakesh;
Suneel, A. Sai;
Rajeswari, V. Raja;
Rani, M. Janaki;
Singh, Richa

Publication type:

Article

Energy-Efficient High Speed Quantum-Dot Cellular Automata (QCA) based Reversible Full Adders for Low-Power Digital Computing Applications.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 91, doi. 10.31838/jvcs/06.02.10

By:

Salameh, Anas A.;
Mohamed, Othman

Publication type:

Article

Design and Performance Analysis of Adiabatic Logic Circuits Using FinFET Technology.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 84, doi. 10.31838/jvcs/06.02.09

By:

Salameh, Anas A.;
Mohamed, Othman

Publication type:

Article

Reversible Vedic Direct Flag Divider in Key Generation of RSA Cryptography.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 75, doi. 10.31838/jvcs/06.02.08

By:

Udhayakumar A.;
Ramya K. C.;
Vijayakumar P.;
Sheeba Rani S.;
Balamanikandan A.;
Saranya K.

Publication type:

Article

Transforming Economic Development through VLSI Technology in the Era of Digitalization.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 65, doi. 10.31838/jvcs/06.02.07

By:

Yaremko, Halyna;
Stoliarchuk, Lesia;
Huk, Liudmyla;
Zapotichna, Maria;
Drapaliuk, Halyna

Publication type:

Article

A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 31, doi. 10.31838/jvcs/06.02.04

By:

Ibrahim, Nadim;
Rajalakshmi, N. R.;
Hammadeh, Karam

Publication type:

Article

Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 40, doi. 10.31838/jvcs/06.02.05

By:

Naidu, T. M. Praneeth;
Sekhar, P. Chandra;
Boya, Pradeep Kumar

Publication type:

Article

Design of Novel High Speed Energy Efficient Robust 4:2 Compressor.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 53, doi. 10.31838/jvcs/06.02.05

By:

Rajput, Anju;
Kumawat, Renu;
Sharma, Jyoti;
Srinivasulu, Avireni

Publication type:

Article

RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 23, doi. 10.31838/jvcs/06.02.03

By:

Sathwik, Bandi;
Sudha, D.;
Devi, Y. Aruna Suhasini;
Bodapati, Jagadeesh

Publication type:

Article

Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 14, doi. 10.31838/jvcs/06.02.02

By:

Botla, Arunalatha;
Durga, G. Kanaka;
Paidimarry, Chandrasekhar

Publication type:

Article

Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 1, doi. 10.31838/jvcs/06.02.01

By:

Ravikumar, G.;
Venkatareddy, D.;
Asharani, M.

Publication type:

Article