Works matching IS 25821458 AND DT 2024 AND VI 6 AND IP 2
Results: 15
VLSI Architecture-Based Implementation of Motion Estimation Algorithm for Underwater Robot Vision System.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 115, doi. 10.31838/jvcs/06.02.13
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Performance Evaluation of Mesh, Spidergon, and Mesh of Spidergon (MoS) Topologies in Network-on-Chip (NoC) Architecture.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 130, doi. 10.31838/jvcs/06.02.15
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Thermometer Coding-Based Application-Specific Efficient Mod Adder for Residue Number Systems.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 122, doi. 10.31838/jvcs/06.02.14
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Implementation of VLSI Systems Incorporating Advanced Cryptography Model for FPGA-IoT Application.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 107, doi. 10.31838/jvcs/06.02.12
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VLSI-Based MED-MEC Architecture for Enhanced IoT Wireless Sensor Networks.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 99, doi. 10.31838/jvcs/06.02.11
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Energy-Efficient High Speed Quantum-Dot Cellular Automata (QCA) based Reversible Full Adders for Low-Power Digital Computing Applications.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 91, doi. 10.31838/jvcs/06.02.10
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Design and Performance Analysis of Adiabatic Logic Circuits Using FinFET Technology.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 84, doi. 10.31838/jvcs/06.02.09
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Reversible Vedic Direct Flag Divider in Key Generation of RSA Cryptography.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 75, doi. 10.31838/jvcs/06.02.08
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Transforming Economic Development through VLSI Technology in the Era of Digitalization.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 65, doi. 10.31838/jvcs/06.02.07
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A Novel Machine Learning Model for Early Detection of Advanced Persistent Threats Utilizing Semi-Synthetic Network Traffic Data.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 31, doi. 10.31838/jvcs/06.02.04
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Low Power System on Chip Implementation of Adaptive Intra Frame and Hierarchical Motion.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 40, doi. 10.31838/jvcs/06.02.05
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Design of Novel High Speed Energy Efficient Robust 4:2 Compressor.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 53, doi. 10.31838/jvcs/06.02.05
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RoBA Multiplier-Driven FIR Filter Synthesis: Uniting Efficiency and Speed for Enhanced Digital Signal Processing.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 23, doi. 10.31838/jvcs/06.02.03
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Development of Low Power GNSS correlator in Zynq SoC for GPS and GLONSS.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 14, doi. 10.31838/jvcs/06.02.02
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Development of Synthesizable Filter-Centric Loop Filter Design for ADPLL Architecture in SoC.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 2, p. 1, doi. 10.31838/jvcs/06.02.01
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