Works matching IS 25821458 AND DT 2024 AND VI 6 AND IP 1
Results: 9
Design and VLSI implementation of SAR Analog to Digital Converter Using Analog Mixed Signal.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 55, doi. 10.31838/jvcs/06.01.05
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A Low Power Adiabatic Approach for Scaled VLSI Circuits.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 1, doi. 10.31838/jvcs/06.01.01
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51 Smart Ways to Catch the Abutment DRCs at IP Level.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 51, doi. 10.31838/jvcs/06.01.08
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Low Power Embedded SoC Design.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 25, doi. 10.31838/jvcs/06.01.04
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1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 19, doi. 10.31838/jvcs/06.01.03
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Detection of Soft Errors in Clock Synthesizers and Latency Reduction Throgh Voltage Scaling Mechanism.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 43, doi. 10.31838/jvcs/06.01.08
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A Hybrid Optical-Acoustic Modem Based on Mimo-Ofdm for Reliable Data Transmission in Green Underwater Wireless Communication.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 36, doi. 10.31838/jvcs/06.01.06
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Desing of VLSI Architecture for a flexible testbed of Artificial Neural Network for training and testing on FPGA.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 30, doi. 10.31838/jvcs/06.01.06
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Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications.
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- Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 7, doi. 10.31838/jvcs/06.01.02
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- Article