XOR Module based Adder Applications Design using QCA.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 36, doi. 10.31838/jvcs/05.02.06
- By:
- Publication type:
- Article
Works matching IS 25821458 AND DT 2023 AND VI 5 AND IP 2
Results: 9
1
2
Universal Shift Register: QCA based Novel Technique for Memory Storage Modules.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 15, doi. 10.31838/jvcs/05.02.03
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- Publication type:
- Article
3
FPGA based Digital Filter Design for faster operations.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 56, doi. 10.31838/jvcs/05.02.09
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- Publication type:
- Article
4
Digital Filter Design: Novel Multiplier Realization.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 43, doi. 10.31838/jvcs/05.02.07
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- Publication type:
- Article
5
FPGA Application: Realization of IIR filter based Architecture.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 29, doi. 10.31838/jvcs/05.02.05
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- Publication type:
- Article
6
CSA Implementation Using Novel Methodology: RTL Development.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 22, doi. 10.31838/jvcs/05.02.04
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- Publication type:
- Article
7
Next Generation Semiconductor based Fundamental Computation Module Implementation.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 50, doi. 10.31838/jvcs/05.02.08
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- Publication type:
- Article
8
Digital Filter based Adder Module Realization High-Speed Switching Functions.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 8, doi. 10.31838/jvcs/05.02.02
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- Publication type:
- Article
9
Fundamental Digital Module Realization Using RTL Design for Quantum Mechanics.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 2, p. 1, doi. 10.31838/jvcs/05.02.01
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- Publication type:
- Article