Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 14, doi. 10.31838/jvcs/04.02.03
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- Publication type:
- Article
Works matching IS 25821458 AND DT 2022 AND VI 4 AND IP 2
Results: 7
1
2
ADC: Novel Methodology for Code Converter Application for Data Processing.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 46, doi. 10.31838/jvcs/04.02.07
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- Publication type:
- Article
3
Fundamental Code Converter Block Design using Novel CMOS Architectures.
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- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 38, doi. 10.31838/jvcs/04.02.06
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- Article
4
Fundamental Data Seperator using Threshold Logic at Low-Supply Voltages.
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- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 30, doi. 10.31838/jvcs/04.02.05
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- Publication type:
- Article
5
Adaptive And Recursive Vedic Karatsuba Multiplier Using Non Linear Carry Select Adder.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 22, doi. 10.31838/jvcs/04.02.04
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- Publication type:
- Article
6
ASIC Implementation of An Effective Reversible R2B Fft for 5G Technology Using Reversible Logic.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 5, doi. 10.31838/jvcs/04.02.02
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- Publication type:
- Article
7
Design and Development of Intrusion Detection System for Wireless Sensor Network.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2022, v. 4, n. 2, p. 1, doi. 10.31838/jvcs/04.02.01
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- Publication type:
- Article