Design a Low Power and High-Speed Parity Checker using Exclusive--or Gates.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 48, doi. 10.31838/jvcs/03.02.06
- By:
- Publication type:
- Article
Works matching IS 25821458 AND DT 2021 AND VI 3 AND IP 2
Results: 6
1
2
Design A Low Power and High Throughput 130nm Full Adder Utilising Exclusive-OR And Exclusive- NOR Gates.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 42, doi. 10.31838/jvcs/03.02.05
- By:
- Publication type:
- Article
3
Energy Reduction of D-Flipflop Using 130nm CMOS Technology.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 34, doi. 10.31838/jvcs/03.02.04
- By:
- Publication type:
- Article
4
Design Of Clocked Hybrid (D/T) Flipflop Through Air Hole Paradigm Photonic Crystal.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 21, doi. 10.31838/jvcs/03.02.03
- By:
- Publication type:
- Article
5
Design and Performance Analysis of High Speed 8-T Full Adder.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 1, doi. 10.31838/jvcs/03.02.01
- By:
- Publication type:
- Article
6
Design Of Clocked Jk Flip Flop Using Air Hole Structured Photonic Crystal.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 11, doi. 10.31838/jvcs/03.02.02
- By:
- Publication type:
- Article