Works matching IS 25821458 AND DT 2021 AND VI 3 AND IP 2
Results: 6
Design a Low Power and High-Speed Parity Checker using Exclusive--or Gates.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 48, doi. 10.31838/jvcs/03.02.06
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- Article
Design A Low Power and High Throughput 130nm Full Adder Utilising Exclusive-OR And Exclusive- NOR Gates.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 42, doi. 10.31838/jvcs/03.02.05
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- Article
Energy Reduction of D-Flipflop Using 130nm CMOS Technology.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 34, doi. 10.31838/jvcs/03.02.04
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- Article
Design Of Clocked Hybrid (D/T) Flipflop Through Air Hole Paradigm Photonic Crystal.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 21, doi. 10.31838/jvcs/03.02.03
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- Article
Design and Performance Analysis of High Speed 8-T Full Adder.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 1, doi. 10.31838/jvcs/03.02.01
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- Article
Design Of Clocked Jk Flip Flop Using Air Hole Structured Photonic Crystal.
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- Journal of VLSI Circuits & Systems (JVCS), 2021, v. 3, n. 2, p. 11, doi. 10.31838/jvcs/03.02.02
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- Article