Measurement Results of Real Circuit Delay Degradation under Realistic Workload.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 27, doi. 10.2197/ipsjtsldm.16.27
- By:
- Publication type:
- Article
Works matching IS 18826687 AND DT 2023 AND VI 16 AND IP 1
Results: 6
1
2
Message from the Editor-in-Chief.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 1, doi. 10.2197/ipsjtsldm.16.1
- By:
- Publication type:
- Article
3
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 45, doi. 10.2197/ipsjtsldm.16.45
- By:
- Publication type:
- Article
4
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 35, doi. 10.2197/ipsjtsldm.16.35
- By:
- Publication type:
- Article
5
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 12, doi. 10.2197/ipsjtsldm.16.12
- By:
- Publication type:
- Article
6
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection.
- Published in:
- IPSJ Transactions on System LSI Design Methodology, 2023, v. 16, n. 1, p. 2, doi. 10.2197/ipsjtsldm.16.2
- By:
- Publication type:
- Article