Erratum: 'Highly adaptive and deadlock‐free routing for three‐dimensional networks‐on‐chip'.
- Published in:
- 2016
- Publication type:
- Correction Notice
Works matching IS 17518601 AND DT 2016 AND VI 10 AND IP 1
Results: 6
1
2
Adaptively weighted round‐robin arbitration for equality of service in a many‐core network‐on‐chip.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2016, v. 10, n. 1, p. 37, doi. 10.1049/iet-cdt.2015.0049
- By:
- Publication type:
- Article
3
Majority‐based evolution state assignment algorithm for area and power optimisation of sequential circuits.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2016, v. 10, n. 1, p. 30, doi. 10.1049/iet-cdt.2015.0038
- By:
- Publication type:
- Article
4
Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2<sup>m</sup>).
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2016, v. 10, n. 1, p. 18, doi. 10.1049/iet-cdt.2015.0020
- By:
- Publication type:
- Article
5
Static test compaction for circuits with multiple independent scan chains.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2016, v. 10, n. 1, p. 12, doi. 10.1049/iet-cdt.2014.0191
- By:
- Publication type:
- Article
6
Accuracy‐aware processor customisation for fixed‐point arithmetic.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2016, v. 10, n. 1, p. 1, doi. 10.1049/iet-cdt.2014.0188
- By:
- Publication type:
- Article