Works matching IS 17518601 AND DT 2015 AND VI 9 AND IP 5
Results: 5
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 5, p. 259, doi. 10.1049/iet-cdt.2014.0151
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- Article
Optimisation of test architecture in three‐dimensional stacked integrated circuits for partial stack/complete stack using hard system‐on‐chips.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 5, p. 268, doi. 10.1049/iet-cdt.2014.0137
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- Article
Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 5, p. 239, doi. 10.1049/iet-cdt.2014.0102
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- Article
Cluster‐based approach for improving graphics processing unit performance by inter streaming multiprocessors locality.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 5, p. 275, doi. 10.1049/iet-cdt.2014.0092
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- Article
Reducing the system standby power of a personal computer.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2015, v. 9, n. 5, p. 248, doi. 10.1049/iet-cdt.2013.0137
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- Article