Found: 18
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Relay‐based identification of Wiener model.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 398, doi. 10.1049/iet-cds.2019.0436
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Design and optimisation of a novel structure capacitive RF MEMS switch to integrate with an antenna to improve its performance parameters.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 276, doi. 10.1049/iet-cds.2019.0425
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6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 340, doi. 10.1049/iet-cds.2019.0421
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Dual band stop filter design via frequency transformation and synthesis with lumped resonators.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 311, doi. 10.1049/iet-cds.2019.0411
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- Article
Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 327, doi. 10.1049/iet-cds.2019.0409
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- Article
11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier‐based stages in 65 nm bulk CMOS.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 322, doi. 10.1049/iet-cds.2019.0377
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Accelerating low‐voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 294, doi. 10.1049/iet-cds.2019.0374
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Flexible structures of lightweight block ciphers PRESENT, SIMON and LED.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 369, doi. 10.1049/iet-cds.2019.0363
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Reduction of Drain Induced Barrier Lowering in DM‐HD‐NA GAAFET for RF Applications.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 270, doi. 10.1049/iet-cds.2019.0306
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Parallel architecture of power‐of‐two multipliers for FPGAs.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 381, doi. 10.1049/iet-cds.2019.0246
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- Article
Design approach to improve the performance of JAMFETs.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 333, doi. 10.1049/iet-cds.2019.0208
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Exploiting uncertain timing information in time‐based SAR ADCs.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 390, doi. 10.1049/iet-cds.2019.0165
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- Article
High‐speed energy efficient process, voltage and temperature tolerant hybrid multi‐threshold 4:2 compressor design in CNFET technology.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 357, doi. 10.1049/iet-cds.2019.0105
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Supervised learning for early and accurate battery terminal voltage collapse detection.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 347, doi. 10.1049/iet-cds.2019.0092
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- Article
Suppression of ambipolarity in tunnel‐FETs using gate oxide as parameter: analysis and investigation.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 288, doi. 10.1049/iet-cds.2019.0053
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65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 303, doi. 10.1049/iet-cds.2019.0028
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8‐bit serialised architecture of SEED block cipher for constrained devices.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 316, doi. 10.1049/iet-cds.2018.5354
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Design and development of symmetrical super‐lift DC–AC converter using firefly algorithm for solar‐photovoltaic applications.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2020, v. 14, n. 3, p. 261, doi. 10.1049/iet-cds.2018.5292
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