Noise‐based logic locking scheme against signal probability skew analysis.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 279, doi. 10.1049/cdt2.12022
- By:
- Publication type:
- Article
Works matching IS 1751-8601 AND VI 15 AND IP 4 AND DT 2021
Results: 6
1
2
Static power model for CMOS and FPGA circuits.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 263, doi. 10.1049/cdt2.12021
- By:
- Publication type:
- Article
3
Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 241, doi. 10.1049/cdt2.12019
- By:
- Publication type:
- Article
4
Homeland security video surveillance system utilising the internet of video things for smart cities.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 302, doi. 10.1049/cdt2.12014
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- Publication type:
- Article
5
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 296, doi. 10.1049/cdt2.12010
- By:
- Publication type:
- Article
6
New scan compression approach to reduce the test data volume.
- Published in:
- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 4, p. 251, doi. 10.1049/cdt2.12020
- By:
- Publication type:
- Article