Assessment and Characterization of Stress Induced by Via-First TSV Technology.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 129, doi. 10.4071/imaps.313
- By:
- Publication type:
- Article
Works matching IS 1551-4897 AND VI 8 AND IP 4 AND DT 2011
Results: 6
1
2
Planar Double-Sided Anode Supported SOFC - Novel Design.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 164, doi. 10.4071/imaps.312
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- Publication type:
- Article
3
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration.
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- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 140, doi. 10.4071/imaps.307
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- Publication type:
- Article
4
Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW).
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 171, doi. 10.4071/imaps.306
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- Publication type:
- Article
5
System-on-Chip Integrated MEMS Packages for RF LNA Testing and Self-Calibration.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 154, doi. 10.4071/imaps.302
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- Publication type:
- Article
6
A Comparison of Back Grinding Processes for Bare Silicon and Through-Silicon Via Wafers Using Numerical Simulations.
- Published in:
- Journal of Microelectronic & Electronic Packaging, 2011, v. 8, n. 4, p. 146, doi. 10.4071/imaps.298
- By:
- Publication type:
- Article