Works matching IS 1535864X AND DT 2013 AND VI 17 AND IP 1

Results: 12

AN INTEGRATED SIMULATION INFRASTRUCTURE FOR THE ENTIRE MEMORY HIERARCHY: CACHE , DRAM, NONVOLATI LE MEMORY, AND DISK.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 184

By:

Stevens, Jim;
Tschirhart, Paul;
Mu-Tien Chang;
Bhati, Ishwar;
Enns, Peter;
Greensky, James;
Chisti, Zeshan;
Shih-Lien Lu;
Jacob, Bruce

Publication type:

Article

A CASE FOR NONUNIFORM FAULT TOLERANCE IN EMERGING MEMORIES.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 166

By:

Qureshi, Moinuddin K.

Publication type:

Article

ERROR ANALYSIS AND RETENTION-AWARE ERROR MANAGEMENT FOR NAND FLASH MEMORY.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 140

By:

Yu Cai;
Yalcin, Gulay;
Mutlu, Onur;
Haratsch, Erich F.;
Crista, Adrian;
Unsal, Osman S.;
Ken Mai

Publication type:

Article

TOWARDS PROPORTIONAL MEMORY SYSTEMS.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 118

By:

Doe Hyun Yoon;
Min Kyu Jeong;
Sullivan, Michael;
Erez, Mattan

Publication type:

Article

MEMORY CONTROLLER-LEVEL EXTENSIONS FOR GDDR5 SINGLE DEVICE DATA CORRECT SUPPORT.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 102

By:

Carretero, Javier;
Hernández, Isaac;
Vera, Xavier;
Juan, Toni;
Herrero, Enric;
Ramírez, Tanusú;
Monchiero, Matteo;
González, Antonio;
Axelos, Nicholas;
Sánchez, Daniel

Publication type:

Article

IMPROVING ERROR CORRECTION IN NAND WITH DOMINANT ERROR PATTERN DETECTION.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 94

By:

Ningde Xie;
Khan, Jawad

Publication type:

Article

ECC TECHNIQUES FOR ENABLING DRAM CACHES WITH OFF-CHIP TAG ARRAYS.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 76

By:

Wei Wu;
Shih-Lien Lu;
Somasekhar, Dinesh;
Agarwal, Rajat

Publication type:

Article

STTRAM SCALING AND RETENTION FAILURE.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 54

By:

Naeimi, Helia;
Augustine, Charles;
Raychowdhury, Arijit;
Shih-Lien Lu;
Tschanz, James

Publication type:

Article

IMPROVING MEMORY RELIABILITY, POWER AND PERFORMANCE USING MIXED-CELL DESIGNS.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 36

By:

Alameldeen, Alaa R.;
Nam Sung Kim;
Khan, Samira M.;
Ghasemi, Hamid Reza;
Wilkerson, Chris;
Kulkarni, Jaydeep;
Jiménez, Daniel A.

Publication type:

Article

SCALING THE MEMORY RELIABILITY WALL.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 18

By:

Wilkerson, Chris;
Alameldeen, Alaa;
Chishti, Zeshan

Publication type:

Article

OVERVIEW.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 10

By:

Held, James P.

Publication type:

Article

Forward ... A Foreword.

Published in:

Intel Technology Journal, 2013, v. 17, n. 1, p. 7

By:

Jacob, Bruce

Publication type:

Article