Works matching IS 14505843 AND DT 2018 AND VI 22 AND IP 1
Results: 5
An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic.
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- Electronics / Elektronika (1450-5843), 2018, v. 22, n. 1, p. 38, doi. 10.7251/ELS1721038M
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- Article
Statistical Analysis of Multiple Access Interference in Chaotic Spreading Sequence Based DS-CDMA Systems.
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- Electronics / Elektronika (1450-5843), 2018, v. 22, n. 1, p. 34, doi. 10.7251/ELS1721034L
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- Article
CFOA-Based Fractional Order PI<sup>λ</sup>D<sup>δ</sup> Controller.
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- Electronics / Elektronika (1450-5843), 2018, v. 22, n. 1, p. 25, doi. 10.7251/ELS1721025C
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- Article
Efficient Computerized-Tomography Reconstruction Using Low-Cost FPGA-DSP Chip.
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- Electronics / Elektronika (1450-5843), 2018, v. 22, n. 1, p. 12, doi. 10.7251/ELS1721012A
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- Article
LUT Based Generalized Parallel Counters for State-of-art FPGAs.
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- Electronics / Elektronika (1450-5843), 2018, v. 22, n. 1, p. 3, doi. 10.7251/ELS1721003K
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- Article