An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic.
- Published in:
- Electronics / Elektronika (1450-5843), 2017, v. 21, n. 1, p. 38, doi. 10.7251/ELS1721038M
- By:
- Publication type:
- Article
Works matching IS 14505843 AND DT 2017 AND VI 21 AND IP 1
Results: 5
1
2
Statistical Analysis of Multiple Access Interference in Chaotic Spreading Sequence Based DS-CDMA Systems.
- Published in:
- Electronics / Elektronika (1450-5843), 2017, v. 21, n. 1, p. 34, doi. 10.7251/ELS1721034L
- By:
- Publication type:
- Article
3
CFOA-Based Fractional Order PI<sup>λ</sup>D<sup>δ</sup> Controller.
- Published in:
- Electronics / Elektronika (1450-5843), 2017, v. 21, n. 1, p. 25, doi. 10.7251/ELS1721025C
- By:
- Publication type:
- Article
4
LUT Based Generalized Parallel Counters for State-of-art FPGAs.
- Published in:
- Electronics / Elektronika (1450-5843), 2017, v. 21, n. 1, p. 3, doi. 10.7251/ELS1721003K
- By:
- Publication type:
- Article
5
Efficient Computerized-Tomography Reconstruction Using Low-Cost FPGA-DSP Chip.
- Published in:
- Electronics / Elektronika (1450-5843), 2017, v. 21, n. 1, p. 12, doi. 10.7251/ELS1721012A
- By:
- Publication type:
- Article