Works matching IS 1065514X AND DT 2002 AND VI 15 AND IP 3
Results: 11
Timing Analysis and Optimization for DSM IC--Guest Editorial.
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- VLSI Design, 2002, v. 15, n. 3, p. 555, doi. 10.1080/1065514021000012174
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- Article
Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis.
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- VLSI Design, 2002, v. 15, n. 3, p. 647, doi. 10.1080/1065514021000012264
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- Article
Improving the Timing of Extended Finite State Machines Via Catalyst.
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- VLSI Design, 2002, v. 15, n. 3, p. 629, doi. 10.1080/1065514021000012246
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- Article
Timing Challenges for Very Deep Sub-Micron (VDSM) IC.
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- VLSI Design, 2002, v. 15, n. 3, p. 557, doi. 10.1080/1065514021000012183
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- Article
Energy Efficient Signaling in Deep-submicron Technology.
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- VLSI Design, 2002, v. 15, n. 3, p. 563, doi. 10.1080/1065514021000012192
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- Article
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation.
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- VLSI Design, 2002, v. 15, n. 3, p. 605, doi. 10.1080/1065514021000012228
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- Article
Timing-Driven-Testable Convergent Tree Adders.
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- VLSI Design, 2002, v. 15, n. 3, p. 637, doi. 10.1080/1065514021000012255
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- Article
A New Characterization Method for Delay and Power Dissipation of Standard Library Cells.
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- VLSI Design, 2002, v. 15, n. 3, p. 667, doi. 10.1080/1065514021000012273
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- Article
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.
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- VLSI Design, 2002, v. 15, n. 3, p. 587, doi. 10.1080/1065514021000012200
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- Publication type:
- Article
CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.
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- VLSI Design, 2002, v. 15, n. 3, p. 619, doi. 10.1080/1065514021000012237
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- Article
Performance Driven Global Routing Through Gradual Refinement.
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- VLSI Design, 2002, v. 15, n. 3, p. 595, doi. 10.1080/1065514021000012219
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- Publication type:
- Article