Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 259, doi. 10.1080/10655140290011069
- By:
- Publication type:
- Article
Works matching IS 1065514X AND DT 2002 AND VI 14 AND IP 3
Results: 7
1
2
Maximizing Memory Data Reuse for Lower Power Motion Estimation.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 299, doi. 10.1080/10655140290011096
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- Publication type:
- Article
3
Low-power Application-specific Parallel Array Multiplier Design for DSP Applications.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 287, doi. 10.1080/10655140290011087
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- Publication type:
- Article
4
Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 249, doi. 10.1080/10655140290011050
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- Publication type:
- Article
5
Identification of Disjoint Bi-decompositions in Boolean Functions through Walsh Spectrum.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 307, doi. 10.1080/10655140290011104
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- Publication type:
- Article
6
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 273, doi. 10.1080/10655140290011078
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- Publication type:
- Article
7
An Algorithm Visualization Tool on the Reconfigurable Mesh.
- Published in:
- VLSI Design, 2002, v. 14, n. 3, p. 239, doi. 10.1080/10655140290011041
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- Publication type:
- Article