Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/987209
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- Publication type:
- Article
Works in VLSI Design, 2012
Results: 37
1
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Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/948957
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- Publication type:
- Article
3
Design Space of Flexible Multigigabit LDPC Decoders.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/942893
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- Publication type:
- Article
4
A SystematicMethodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/784945
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- Publication type:
- Article
5
N Point DCT VLSI Architecture for Emerging HEVC Standard.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/752024
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- Publication type:
- Article
6
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/748019
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- Publication type:
- Article
7
Power Consumption Models for Decimation FIR Filters in Multistandard Receivers.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/870546
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- Publication type:
- Article
8
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/794753
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- Publication type:
- Article
9
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/793196
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- Publication type:
- Article
10
Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/849120
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- Publication type:
- Article
11
A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/826350
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- Publication type:
- Article
12
A ±6ms-Accuracy, 0.68 mm<sup>2</sup>, and 2.21 μW QRS Detection ASIC.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/809393
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- Publication type:
- Article
13
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/745861
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- Publication type:
- Article
14
Flexible LDPC Decoder Architectures.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/730835
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- Publication type:
- Article
15
Cognitive Radio RF: Overview and Challenges.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/716476
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- Publication type:
- Article
16
Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/657897
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- Publication type:
- Article
17
FastRoute: An Efficient and High-Quality Global Router.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/608362
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- Publication type:
- Article
18
Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/602737
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- Publication type:
- Article
19
Line Search-Based Inverse Lithography Technique for Mask Design.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/589128
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- Publication type:
- Article
20
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/580584
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- Publication type:
- Article
21
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/575389
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- Publication type:
- Article
22
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/549768
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- Publication type:
- Article
23
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/546212
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- Publication type:
- Article
24
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/505983
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- Publication type:
- Article
25
Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/450302
- By:
- Publication type:
- Article
26
An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/413747
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- Publication type:
- Article
27
A New Length-Based Algebraic Multigrid Clustering Algorithm.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/395260
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- Publication type:
- Article
28
A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/312808
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- Publication type:
- Article
29
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/298396
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- Publication type:
- Article
30
A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/273276
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- Publication type:
- Article
31
Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM AlgorithmMapped onto Systolic Array.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/268402
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- Publication type:
- Article
32
9T Full Adder Design in Subthreshold Region.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/248347
- By:
- Publication type:
- Article
33
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/209208
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- Publication type:
- Article
34
A Signature-Based Power Model for MPSoC on FPGA.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/196984
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- Publication type:
- Article
35
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/173079
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- Publication type:
- Article
36
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards.
- Published in:
- 2012
- By:
- Publication type:
- Editorial
37
Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC.
- Published in:
- VLSI Design, 2012, p. 1, doi. 10.1155/2012/242989
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- Publication type:
- Article