Works matching IS 10648887 AND DT 2013 AND VI 55 AND IP 11


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    Delay testable logical circuit design.

    Published in:
    Russian Physics Journal, 2013, v. 55, n. 11, p. 1370, doi. 10.1007/s11182-013-9969-8
    By:
    • Matrosova, A.;
    • Nikolaeva, E.;
    • Rumyantseva, E.
    Publication type:
    Article
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