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Works matching IS 09739238 AND DT 2014 AND VI 8 AND IP 1

Results: 3

1

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime.

Published in:

International Journal on Intelligent Electronics Systems, 2014, v. 8, n. 1, p. 8, doi. 10.18000/ijies.30133

By:

Bhargava, Bhanupriya;
Sharma, Pradeep Kumar;
Akashe, Shyam

Publication type:

Article

2

MODIFIED BYPASSING MULTIPLIER FOR POWER EFFICIENT FIR FILTER.

Published in:

International Journal on Intelligent Electronics Systems, 2014, v. 8, n. 1, p. 1, doi. 10.18000/ijies.30132

By:

Daniel, Anita;
Selvarasu, N.

Publication type:

Article

3

ANALYSIS OF 3D FACE RECONSTRUCTION.

Published in:

International Journal on Intelligent Electronics Systems, 2014, v. 8, n. 1, p. 14, doi. 10.18000/ijies.30134

By:

Ramasubramanian, M.;
Rangaswamy, M. A. Dorai

Publication type:

Article