An Integrated Framework for Application Independent Testing of FPGA Interconnect.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 729, doi. 10.1007/s10836-019-05827-7
- By:
- Publication type:
- Article
Works matching IS 09238174 AND DT 2019 AND VI 35 AND IP 5
Results: 15
1
2
Editorial.
- Published in:
- 2019
- By:
- Publication type:
- Editorial
3
Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness.
- Published in:
- 2019
- By:
- Publication type:
- Correction Notice
4
Classical Cryptanalysis Attacks on Logic Locking Techniques.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 641, doi. 10.1007/s10836-019-05838-4
- By:
- Publication type:
- Article
5
Guest Editorial.
- Published in:
- 2019
- By:
- Publication type:
- Editorial
6
Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 605, doi. 10.1007/s10836-019-05826-8
- By:
- Publication type:
- Article
7
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 715, doi. 10.1007/s10836-019-05828-6
- By:
- Publication type:
- Article
8
2018 JETTA-TTTC Best Paper Award: Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin and Masaki Hashizume, "Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories,"Journal of Electronic Testing: Theory and Applications, Volume 34, Number 4, pp. 435–446, August 2018
- Published in:
- 2019
- Publication type:
- Announcement
9
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 679, doi. 10.1007/s10836-019-05831-x
- By:
- Publication type:
- Article
10
RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 695, doi. 10.1007/s10836-019-05825-9
- By:
- Publication type:
- Article
11
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 741, doi. 10.1007/s10836-019-05824-w
- By:
- Publication type:
- Article
12
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 655, doi. 10.1007/s10836-019-05830-y
- By:
- Publication type:
- Article
13
Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 581, doi. 10.1007/s10836-019-05829-5
- By:
- Publication type:
- Article
14
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 577, doi. 10.1007/s10836-019-05822-y
- Publication type:
- Article
15
A State Machine Encoding Methodology Against Power Analysis Attacks.
- Published in:
- Journal of Electronic Testing, 2019, v. 35, n. 5, p. 621, doi. 10.1007/s10836-019-05821-z
- By:
- Publication type:
- Article