Works matching IS 09238174 AND DT 2019 AND VI 35 AND IP 1

Results: 13

An Optimized NS2 Module for UHF Passive RFID Systems.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 45, doi. 10.1007/s10836-018-5769-y

By:

Benfraj, Rahma;
Beroulle, Vincent;
Fourty, Nicolas;
Meddeb, Aref

Publication type:

Article

Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 119, doi. 10.1007/s10836-019-05774-3

By:

Taghipour, Shiva;
Niaraki Asli, Rahebeh

Publication type:

Article

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 59, doi. 10.1007/s10836-019-05776-1

By:

Karel, Amit;
Azaïs, Florence;
Comte, Mariane;
Gallière, Jean-Marc;
Renovell, Michel

Publication type:

Article

Editorial.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 1, doi. 10.1007/s10836-019-05781-4

By:

Agrawal, Vishwani D.

Publication type:

Article

Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 77, doi. 10.1007/s10836-019-05780-5

By:

Ahmad, Shakeel;
Dąbrowski, Jerzy

Publication type:

Article

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 29, doi. 10.1007/s10836-019-05779-y

By:

Avramenko, Serhiy;
Violante, Massimo

Publication type:

Article

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 9, doi. 10.1007/s10836-019-05778-z

By:

Villa, Paulo R. C.;
Travessini, Rodrigo;
Goerl, Roger C.;
Vargas, Fabian L.;
Bezerra, Eduardo A.

Publication type:

Article

Metric-Driven Verification Methodology with Regression Management.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 101, doi. 10.1007/s10836-019-05777-0

By:

Cieplucha, Marek

Publication type:

Article

2018JETTAReviewers.

Published in:: Journal of Electronic Testing, 2019, v. 35, n. 1, p. 5, doi. 10.1007/s10836-019-05775-2
Publication type:: Article

A Layout-Based Rad-Hard DICE Flip-Flop Design.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 111, doi. 10.1007/s10836-019-05773-4

By:

Wang, Haibin;
Dai, Xixi;
Ibrahim, Younis Mohammed Younis;
Sun, Hongwen;
Nofal, Issam;
Cai, Li;
Guo, Gang;
Shen, Zicai;
Chen, Li

Publication type:

Article

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 1, p. 87, doi. 10.1007/s10836-019-05772-5

By:

Gomez, Andres;
Champac, Victor

Publication type:

Article

New Editors - 2019.

Published in:: Journal of Electronic Testing, 2019, v. 35, n. 1, p. 3, doi. 10.1007/s10836-019-05771-6
Publication type:: Article

Test Technology Newsletter.

Published in:: Journal of Electronic Testing, 2019, v. 35, n. 1, p. 7, doi. 10.1007/s10836-018-05770-z
Publication type:: Article