Works matching IS 09238174 AND DT 2018 AND VI 34 AND IP 1
Results: 10
Editorial.
- Published in:
- 2018
- By:
- Publication type:
- Editorial
<bold>New Editor - 2018</bold>.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 3, doi. 10.1007/s10836-018-5711-3
- Publication type:
- Article
Automation of Test Program Synthesis for Processor Post-silicon Validation.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 83, doi. 10.1007/s10836-018-5709-x
- By:
- Publication type:
- Article
NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 27, doi. 10.1007/s10836-018-5707-z
- By:
- Publication type:
- Article
Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 67, doi. 10.1007/s10836-018-5706-0
- By:
- Publication type:
- Article
Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 43, doi. 10.1007/s10836-018-5705-1
- By:
- Publication type:
- Article
Test Technology Newsletter.
- Published in:
- 2018
- Publication type:
- Proceeding
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 53, doi. 10.1007/s10836-018-5703-3
- By:
- Publication type:
- Article
FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 15, doi. 10.1007/s10836-017-5702-9
- By:
- Publication type:
- Article
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 7, doi. 10.1007/s10836-017-5701-x
- By:
- Publication type:
- Article