Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 491, doi. 10.1007/s10836-015-5547-z
- By:
- Publication type:
- Article
Works matching IS 09238174 AND DT 2015 AND VI 31 AND IP 5/6
Results: 13
1
2
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 443, doi. 10.1007/s10836-015-5548-y
- By:
- Publication type:
- Article
3
Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog Filters.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 461, doi. 10.1007/s10836-015-5543-3
- By:
- Publication type:
- Article
4
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 427, doi. 10.1007/s10836-015-5546-0
- By:
- Publication type:
- Article
5
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 479, doi. 10.1007/s10836-015-5545-1
- By:
- Publication type:
- Article
6
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 525, doi. 10.1007/s10836-015-5544-2
- By:
- Publication type:
- Article
7
Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 561, doi. 10.1007/s10836-015-5549-x
- By:
- Publication type:
- Article
8
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 503, doi. 10.1007/s10836-015-5541-5
- By:
- Publication type:
- Article
9
2014 JETTA-TTTC Best Paper Award.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 425, doi. 10.1007/s10836-015-5552-2
- Publication type:
- Article
10
Design and Implementation of an FPGA-Based Data/Timing Formatter.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 549, doi. 10.1007/s10836-015-5554-0
- By:
- Publication type:
- Article
11
Editorial.
- Published in:
- 2015
- By:
- Publication type:
- Editorial
12
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 423, doi. 10.1007/s10836-015-5550-4
- Publication type:
- Article
13
Double Node Upsets Hardened Latch Circuits.
- Published in:
- Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 537, doi. 10.1007/s10836-015-5551-3
- By:
- Publication type:
- Article