Works matching IS 09238174 AND DT 2013 AND VI 29 AND IP 6

Results: 14

Test Technology Newsletter.

Published in:: Journal of Electronic Testing, 2013, v. 29, n. 6, p. 743, doi. 10.1007/s10836-013-5422-8
Publication type:: Article

Effective Timing Error Tolerance in Flip-Flop Based Core Designs.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 795, doi. 10.1007/s10836-013-5419-3

By:

Valadimas, Stefanos;
Tsiatouhas, Yiorgos;
Arapoyanni, Angela;
Xarchakos, Petros

Publication type:

Article

Selective SWIFT-R: A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 825, doi. 10.1007/s10836-013-5416-6

By:

Restrepo-Calle, Felipe;
Martínez-Álvarez, Antonio;
Cuenca-Asensi, Sergio;
Jimeno-Morenilla, Antonio

Publication type:

Article

A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 805, doi. 10.1007/s10836-013-5420-x

By:

Vavousis, Alexandros;
Apostolakis, Andreas;
Psarakis, Mihalis

Publication type:

Article

Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM Technique.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 893, doi. 10.1007/s10836-013-5414-8

By:

Xia, Tian;
Shetty, Rohit;
Platt, Timothy;
Slamani, Mustapha

Publication type:

Article

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 879, doi. 10.1007/s10836-013-5408-6

By:

Uemori, Satoshi;
Ishii, Masamichi;
Kobayashi, Haruo;
Hirabayashi, Daiki;
Arakawa, Yuta;
Doi, Yuta;
Kobayashi, Osamu;
Matsuura, Tatsuji;
Niitsu, Kiichi;
Yano, Yuji;
Gake, Tatsuhiro;
Yamaguchi, Takahiro J.;
Takai, Nobukazu

Publication type:

Article

Editorial.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 741, doi. 10.1007/s10836-013-5424-6

By:

Agrawal, Vishwani D.

Publication type:

Article

Online Testable Approaches in Reversible Logic.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 763, doi. 10.1007/s10836-013-5399-3

By:

Nayeem, N. M.;
Rice, J. E.

Publication type:

Article

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 849, doi. 10.1007/s10836-013-5415-7

By:

Wu, Tie-Bin;
Liu, Heng-Zhu;
Liu, Peng-Xia

Publication type:

Article

Physics-Based Low-Cost Test Technique for High Voltage LDMOS.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 745, doi. 10.1007/s10836-013-5417-5

By:

Kannan, Sukeshwar;
Kannan, Kaushal;
Kim, Bruce C.;
Taenzler, Friedrich;
Antley, Richard;
Moushegian, Ken;
Butler, Kenneth M.;
Mirizzi, Doug

Publication type:

Article

Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 861, doi. 10.1007/s10836-013-5401-0

By:

Xia, Likun;
Farooq, Muhammad Umer;
Bell, Ian M.;
Hussin, Fawnizu Azmadi;
Malik, Aamir Saeed

Publication type:

Article

Preserving Hamming Distance in Arithmetic and Logical Operations.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 903, doi. 10.1007/s10836-013-5421-9

By:

Dolev, Shlomi;
Frenkel, Sergey;
Tamir, Dan E.;
Sinelnikov, Vladimir

Publication type:

Article

MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 839, doi. 10.1007/s10836-013-5400-1

By:

Koppe, Jefferson P.;
Duarte Jr., Elias P.;
Bona, Luis C. E.

Publication type:

Article

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 779, doi. 10.1007/s10836-013-5418-4

By:

Bolchini, Cristiana;
Miele, Antonio;
Sandionigi, Chiara

Publication type:

Article