Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 521, doi. 10.1007/s10836-013-5397-5
- By:
- Publication type:
- Article
Works matching IS 09238174 AND DT 2013 AND VI 29 AND IP 4
Results: 14
1
2
Neural Network Guided Spatial Fault Resilience in Array Processors.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 473, doi. 10.1007/s10836-013-5394-8
- By:
- Publication type:
- Article
3
A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 585, doi. 10.1007/s10836-013-5380-1
- By:
- Publication type:
- Article
4
An Approximate Calculation of Ratio of Normal Variables and Its Application in Analog Circuit Fault Diagnosis.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 555, doi. 10.1007/s10836-013-5382-z
- By:
- Publication type:
- Article
5
Prognostics of Analog Filters Based on Particle Filters Using Frequency Features.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 567, doi. 10.1007/s10836-013-5383-y
- By:
- Publication type:
- Article
6
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 545, doi. 10.1007/s10836-013-5392-x
- By:
- Publication type:
- Article
7
Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 609, doi. 10.1007/s10836-013-5379-7
- By:
- Publication type:
- Article
8
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 455, doi. 10.1007/s10836-013-5395-7
- Publication type:
- Article
9
A Fault Tolerant Hierarchical Network on Chip Router Architecture.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 485, doi. 10.1007/s10836-013-5398-4
- By:
- Publication type:
- Article
10
Process-Variation and Temperature Aware SoC Test Scheduling Technique.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 499, doi. 10.1007/s10836-013-5374-z
- By:
- Publication type:
- Article
11
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 537, doi. 10.1007/s10836-013-5384-x
- By:
- Publication type:
- Article
12
Memory Reliability Improvement Based on Maximized Error-Correcting Codes.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 601, doi. 10.1007/s10836-013-5396-6
- By:
- Publication type:
- Article
13
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.
- Published in:
- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 457, doi. 10.1007/s10836-013-5393-9
- By:
- Publication type:
- Article
14
Editorial.
- Published in:
- 2013
- By:
- Publication type:
- Editorial