Works matching IS 09238174 AND DT 2013 AND VI 29 AND IP 3

Results: 16

A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 275, doi. 10.1007/s10836-013-5357-0

By:

Shi, Yiwen;
Dworak, Jennifer

Publication type:

Article

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 431, doi. 10.1007/s10836-013-5389-5

By:

Latif, Khalid;
Rahmani, Amir-Mohammad;
Nigussie, Ethiopia;
Seceleanu, Tiberiu;
Radetzki, Martin;
Tenhunen, Hannu

Publication type:

Article

A Practical Approach to Single Event Transient Analysis for Highly Complex Design.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 301, doi. 10.1007/s10836-013-5385-9

By:

Costenaro, Enrico;
Alexandrescu, Dan;
Belhaddad, Kader;
Nicolaidis, Michael

Publication type:

Article

Test Technology Newsletter.

Published in:: Journal of Electronic Testing, 2013, v. 29, n. 3, p. 257, doi. 10.1007/s10836-013-5381-0
Publication type:: Article

Guest Editorial.

Published in:

2013

By:

Joshi, Prashant;
Violante, Massimo

Publication type:

Editorial

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 331, doi. 10.1007/s10836-013-5359-y

By:

Possamai Bastos, Rodrigo;
Natale, Giorgio;
Flottes, Marie-Lise;
Lu, Feng;
Rouzeyre, Bruno

Publication type:

Article

On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 261, doi. 10.1007/s10836-013-5388-6

By:

Cho, Geunho;
Lombardi, Fabrizio

Publication type:

Article

Editorial.

Published in:

2013

By:

Agrawal, Vishwani

Publication type:

Editorial

A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 415, doi. 10.1007/s10836-013-5377-9

By:

Fukushima, Yusuke;
Fukushi, Masaru;
Yairi, Ikuko

Publication type:

Article

On the Impact of Performance Faults in Modern Microprocessors.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 351, doi. 10.1007/s10836-013-5360-5

By:

Karimi, Naghmeh;
Maniatakos, Michail;
Tirumurti, Chandrasekharan;
Makris, Yiorgos

Publication type:

Article

Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 367, doi. 10.1007/s10836-013-5356-1

By:

Soucarros, Mathilde;
Clédière, Jessy;
Dumas, Cécile;
Elbaz-Vincent, Philippe

Publication type:

Article

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 401, doi. 10.1007/s10836-013-5355-2

By:

Rossi, D.;
Omaña, M.;
Garrammone, G.;
Metra, C.;
Jas, A.;
Galivanche, R.

Publication type:

Article

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 289, doi. 10.1007/s10836-013-5358-z

By:

Vazquez, J.;
Champac, V.;
Semião, J.;
Teixeira, I.;
Santos, M.;
Teixeira, J.

Publication type:

Article

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 341, doi. 10.1007/s10836-013-5387-7

By:

Alderighi, M.;
Casini, F.;
D'Angelo, S.;
Gravina, A.;
Liberali, V.;
Mancini, M.;
Musazzi, P.;
Pastore, S.;
Sassi, M.;
Sorrenti, G.

Publication type:

Article

A Probabilistic Approach to Diagnose SETs in Sequential Circuits.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 317, doi. 10.1007/s10836-013-5361-4

By:

Gangadhar, Sreenivas;
Tragoudas, Spyros

Publication type:

Article

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 383, doi. 10.1007/s10836-013-5386-8

By:

Bonnoit, Thierry;
Nicolaidis, Michael;
Zergainoh, Nacer-Eddine

Publication type:

Article