Optimization Methods for Post-Bond Testing of 3D Stacked ICs.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 103, doi. 10.1007/s10836-011-5233-8
- By:
- Publication type:
- Article
Works matching IS 09238174 AND DT 2012 AND VI 28 AND IP 1
Results: 15
1
2
Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 53, doi. 10.1007/s10836-011-5242-7
- By:
- Publication type:
- Article
3
Scheduling Tests for 3D Stacked Chips under Power Constraints.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 121, doi. 10.1007/s10836-011-5244-5
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- Publication type:
- Article
4
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 27, doi. 10.1007/s10836-011-5261-4
- By:
- Publication type:
- Article
5
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 93, doi. 10.1007/s10836-011-5262-3
- By:
- Publication type:
- Article
6
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 63, doi. 10.1007/s10836-011-5259-y
- By:
- Publication type:
- Article
7
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 15, doi. 10.1007/s10836-011-5270-3
- By:
- Publication type:
- Article
8
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 39, doi. 10.1007/s10836-011-5263-2
- By:
- Publication type:
- Article
9
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 137, doi. 10.1007/s10836-011-5260-5
- By:
- Publication type:
- Article
10
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 73, doi. 10.1007/s10836-011-5269-9
- By:
- Publication type:
- Article
11
2011 JETTA Reviewers.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 7, doi. 10.1007/s10836-012-5278-3
- Publication type:
- Article
12
New Editors, 2012.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 3, doi. 10.1007/s10836-012-5282-7
- Publication type:
- Article
13
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2012, v. 28, n. 1, p. 11, doi. 10.1007/s10836-012-5280-9
- Publication type:
- Article
14
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits.
- Published in:
- 2012
- By:
- Publication type:
- Editorial
15
Editorial.
- Published in:
- 2012
- By:
- Publication type:
- Editorial