Works matching IS 09238174 AND DT 2008 AND VI 24 AND IP 1-3

Results: 30

Guest Editorial.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 9, doi. 10.1007/s10836-008-5067-1

By:

Nur Touba;
Adelio Salsano;
Minsu Choi

Publication type:

Article

Test Technology Newsletter February 2008.

Published in:: Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 5, doi. 10.1007/s10836-008-5065-3
Publication type:: Article

New Editors.

Published in:: Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 3, doi. 10.1007/s10836-008-5066-2
Publication type:: Article

Editorial.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 1, doi. 10.1007/s10836-008-5069-z

By:

Vishwani Agrawal

Publication type:

Article

Analysis and Evaluations of Reliability of Reconfigurable FPGAs.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 105, doi. 10.1007/s10836-007-5040-4

By:

Salvatore Pontarelli;
Marco Ottavi;
Vamsi Vankamamidi;
Gian Cardarilli;
Fabrizio Lombardi;
Adelio Salsano

Publication type:

Article

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 21, doi. 10.1007/s10836-007-5017-3

By:

Mahdi Fazeli;
Reza Farivar;
Seyed Miremadi

Publication type:

Article

List of 2007 Reviewers.

Published in:: Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 7, doi. 10.1007/s10836-008-5068-0
Publication type:: Article

Design Considerations for High Performance RF Cores Based on Process Variation Study.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 143, doi. 10.1007/s10836-007-5019-1

By:

Shambhu Upadhyaya;
Nandakumar Venugopal;
Nihal Shastry;
Srinivasan Gopalakrishnan;
Bharath Kuppuswamy;
Rana Bhowmick;
Prerna Mayor

Publication type:

Article

A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 259, doi. 10.1007/s10836-007-5024-4

By:

Abhijit Jas;
Yi-Shing Chang;
Sreejit Chakravarty

Publication type:

Article

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 247, doi. 10.1007/s10836-007-5030-6

By:

Zhiyuan He;
Zebo Peng;
Petru Eles;
Paul Rosinger;
Bashir Al-Hashimi

Publication type:

Article

Software and Hardware Techniques for SEU Detection in IP Processors.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 35, doi. 10.1007/s10836-007-5028-0

By:

C. Bolchini;
A. Miele;
M. Rebaudengo;
F. Salice;
D. Sciuto;
L. Sterpone;
M. Violante

Publication type:

Article

Checkersâ No-Harm Alarms and Design Approaches to Tolerate Them.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 93, doi. 10.1007/s10836-007-5031-5

By:

Daniele Rossi;
Martin OmaÃ±a;
Cecilia Metra

Publication type:

Article

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 165, doi. 10.1007/s10836-007-5023-5

By:

Lushan Liu;
Pradeep Nagaraj;
Shambhu Upadhyaya;
Ramalingam Sridhar

Publication type:

Article

Hierarchical Verification for Increasing Performance in Reliable Processors.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 117, doi. 10.1007/s10836-007-5037-z

By:

Joonhyuk Yoo;
Manoj Franklin

Publication type:

Article

Scan Test Response Compaction Combined with Diagnosis Capabilities.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 235, doi. 10.1007/s10836-007-5043-1

By:

Sverre Wichlund;
Frank Berntsen;
Einar Aas

Publication type:

Article

Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 157, doi. 10.1007/s10836-007-5027-1

By:

Kristian Granhaug;
Snorre Aunet

Publication type:

Article

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 203, doi. 10.1007/s10836-007-5020-8

By:

Kyriakos Christou;
Maria Michael;
Spyros Tragoudas

Publication type:

Article

Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 67, doi. 10.1007/s10836-007-5035-1

By:

Amlan Ganguly;
Partha Pande;
Benjamin Belzer;
Cristian Grecu

Publication type:

Article

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 297, doi. 10.1007/s10836-007-5042-2

By:

X. Ma;
J. Huang;
C. Metra;
F. Lombardi

Publication type:

Article

Bilateral Testing of Nano-scale Fault-Tolerant Circuits.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 285, doi. 10.1007/s10836-007-5041-3

By:

Lei Fang;
Michael Hsiao

Publication type:

Article

Substrate Testing on a Multi-Site/Multi-Probe ATE.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 193, doi. 10.1007/s10836-007-5038-y

By:

Xiaojun Ma;
Fabrizio Lombardi

Publication type:

Article

Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X â Y Zoning Method.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 223, doi. 10.1007/s10836-007-5022-6

By:

Yukiya Miura;
Jiro Kato

Publication type:

Article

Monomer Control for Error Tolerance in DNA Self-Assembly.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 271, doi. 10.1007/s10836-007-5016-4

By:

Byunghyun Jang;
Yong-Bin Kim;
Fabrizio Lombardi

Publication type:

Article

Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 313, doi. 10.1007/s10836-007-5052-0

By:

Myungsu Choi;
Minsu Choi

Publication type:

Article

Performance-Optimized Design for Parametric Reliability.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 129, doi. 10.1007/s10836-007-5001-y

By:

Ramyanshu Datta;
Jacob Abraham;
Abdulkadir Utku Diril;
Abhijit Chatterjee;
Kevin Nowka

Publication type:

Article

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 57, doi. 10.1007/s10836-007-5029-z

By:

Rui Gong;
Wei Chen;
Fang Liu;
Kui Dai;
Zhiying Wang

Publication type:

Article

Majority Logic Mapping for Soft Error Dependability.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 83, doi. 10.1007/s10836-007-5044-0

By:

Lorenzo Petroli;
Carlos Lisboa;
Fernanda Kastensmidt;
Luigi Carro

Publication type:

Article

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 45, doi. 10.1007/s10836-007-5018-2

By:

Eduardo Rhod;
Carlos LisbÃ´a;
Luigi Carro;
Matteo Sonza Reorda;
Massimo Violante

Publication type:

Article

A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 181, doi. 10.1007/s10836-007-5032-4

By:

Da-Ming Chang;
Jin-Fu Li;
Yu-Jen Huang

Publication type:

Article

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.

Published in:

Journal of Electronic Testing, 2008, v. 24, n. 1-3, p. 11, doi. 10.1007/s10836-007-5034-2

By:

Yoichi Sasaki;
Kazuteru Namba;
Hideo Ito

Publication type:

Article