Found: 13
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Editorial.
- Published in:
- 2016
- By:
- Publication type:
- Editorial
New Editors - 2016.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 3, doi. 10.1007/s10836-016-5568-2
- Publication type:
- Article
2015 JETTA Reviewers.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 7, doi. 10.1007/s10836-016-5567-3
- Publication type:
- Article
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 9, doi. 10.1007/s10836-016-5564-6
- Publication type:
- Article
A Built-in Single Event Upsets Detector for Sequential Cells.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 11, doi. 10.1007/s10836-015-5560-2
- By:
- Publication type:
- Article
Optimization of a Particles Detection Chain Based on a VCO Structure.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 21, doi. 10.1007/s10836-016-5563-7
- By:
- Publication type:
- Article
Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 31, doi. 10.1007/s10836-016-5565-5
- By:
- Publication type:
- Article
Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 43, doi. 10.1007/s10836-015-5555-z
- By:
- Publication type:
- Article
A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 59, doi. 10.1007/s10836-016-5562-8
- By:
- Publication type:
- Article
SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 69, doi. 10.1007/s10836-015-5556-y
- By:
- Publication type:
- Article
Practical Analog Circuit Diagnosis Based on Fault Features with Minimum Ambiguities.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 83, doi. 10.1007/s10836-015-5561-1
- By:
- Publication type:
- Article
Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 1, p. 97, doi. 10.1007/s10836-015-5559-8
- By:
- Publication type:
- Article
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection.
- Published in:
- 2016
- By:
- Publication type:
- Erratum