High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 3, doi. 10.1007/s11227-006-6719-5
- By:
- Publication type:
- Article
Works matching IS 09208542 AND DT 2006 AND VI 38 AND IP 1
Results: 6
1
2
Work-efficient BSR-based parallel algorithms for some fundamental problems in graph theory.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 83, doi. 10.1007/s11227-006-9157-5
- By:
- Publication type:
- Article
3
A Parallel Implementation of the Katsevich Algorithm for 3-D CT Image Reconstruction.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 35, doi. 10.1007/s11227-006-6675-0
- By:
- Publication type:
- Article
4
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 17, doi. 10.1007/s11227-006-6743-5
- By:
- Publication type:
- Article
5
Addressing a workload characterization study to the design of consistency protocols.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 49, doi. 10.1007/s11227-006-7866-4
- By:
- Publication type:
- Article
6
The p-sized partitioning algorithm for fast computation of factorials of numbers.
- Published in:
- Journal of Supercomputing, 2006, v. 38, n. 1, p. 73, doi. 10.1007/s11227-006-7285-5
- By:
- Publication type:
- Article