Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 149, doi. 10.1023/A:1024447517501
- By:
- Publication type:
- Article
Works matching IS 09208542 AND DT 2003 AND VI 26 AND IP 2
Results: 6
1
2
Instance-Specific Accelerators for Minimum Covering.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 109, doi. 10.1023/A:1024443416592
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- Publication type:
- Article
3
PACT XPP—A Self-Reconfigurable Data Processing Architecture.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 167, doi. 10.1023/A:1024499601571
- By:
- Publication type:
- Article
4
Experience with a Hybrid Processor: K-Means Clustering.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 131, doi. 10.1023/A:1024495400663
- By:
- Publication type:
- Article
5
Engineering of Configurable Systems: Guest Editors Foreword.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 107, doi. 10.1023/A:1024416732522
- By:
- Publication type:
- Article
6
Low Power Encoding Techniques for Dynamically Reconfigurable Hardware.
- Published in:
- Journal of Supercomputing, 2003, v. 26, n. 2, p. 185, doi. 10.1023/A:1024451718410
- By:
- Publication type:
- Article