Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
- Published in:
- International Journal of Parallel Programming, 2007, v. 35, n. 2, p. 157, doi. 10.1007/s10766-006-0030-1
- By:
- Publication type:
- Article
Works matching IS 08857458 AND DT 2007 AND VI 35 AND IP 2
Results: 4
1
2
Fault-aware Communication Mapping for NoCs with Guaranteed Latency.
- Published in:
- International Journal of Parallel Programming, 2007, v. 35, n. 2, p. 125, doi. 10.1007/s10766-006-0029-7
- By:
- Publication type:
- Article
3
Amdahl’s Law Revisited for Single Chip Systems.
- Published in:
- International Journal of Parallel Programming, 2007, v. 35, n. 2, p. 101, doi. 10.1007/s10766-006-0028-8
- By:
- Publication type:
- Article
4
Special Issue On Embedded Processors – Guest Editor Introduction.
- Published in:
- International Journal of Parallel Programming, 2007, v. 35, n. 2, p. 99, doi. 10.1007/s10766-006-0031-0
- By:
- Publication type:
- Article