Orthogonal Ramanujan Sums-based Multirate Filter Bank.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5813, doi. 10.1007/s00034-021-01797-4
- By:
- Publication type:
- Article
Works in Circuits, Systems & Signal Processing, 2021, Vol 40, Issue 11
Results: 31
1
2
Correction to: Asymptotic Properties of Least Squares Estimators and Sequential Least Squares Estimators of a Chirp-like Signal Model Parameters.
- Published in:
- 2021
- By:
- Publication type:
- Correction Notice
3
Novel Double-Dispersion Models Based on Power-Law Filters.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5799, doi. 10.1007/s00034-021-01755-0
- By:
- Publication type:
- Article
4
High Efficient Polyphase Digital Down Converter on FPGA.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5787, doi. 10.1007/s00034-021-01749-y
- By:
- Publication type:
- Article
5
A New High-Speed, Low-Area Residue-to-Binary Converter For the Moduli Set {24n,22n+1,2n+1,2n-1} Based on CRT-1.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5773, doi. 10.1007/s00034-021-01743-4
- By:
- Publication type:
- Article
6
Stability of Switched Systems with Unstable Subsystems: A Sequence-Based Average Dwell Time Approach.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5328, doi. 10.1007/s00034-021-01742-5
- By:
- Publication type:
- Article
7
A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5682, doi. 10.1007/s00034-021-01741-6
- By:
- Publication type:
- Article
8
Adaptive S-Transform with Chirp-Modulated Window and Its Synchroextracting Transform.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5654, doi. 10.1007/s00034-021-01740-7
- By:
- Publication type:
- Article
9
A 300 nW 10 kHz Relaxation Oscillator with 105 ppm/∘C Temperature Coefficient.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5264, doi. 10.1007/s00034-021-01739-0
- By:
- Publication type:
- Article
10
Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5759, doi. 10.1007/s00034-021-01738-1
- By:
- Publication type:
- Article
11
Fractal-Based Speech Analysis for Emotional Content Estimation.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5632, doi. 10.1007/s00034-021-01737-2
- By:
- Publication type:
- Article
12
Resolving Two-Dimensional Ambiguity in Subspace-Based Frequency Estimation for Harmonic Signals.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5616, doi. 10.1007/s00034-021-01736-3
- By:
- Publication type:
- Article
13
Wideband MIMO Radar Transmit Beampattern Synthesis via Majorization–Minimization.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5594, doi. 10.1007/s00034-021-01735-4
- By:
- Publication type:
- Article
14
Model Order Reduction of Positive Real Systems Based on Mixed Gramian Balanced Truncation with Error Bounds.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5309, doi. 10.1007/s00034-021-01734-5
- By:
- Publication type:
- Article
15
2-D Deconvolved Conventional Beamforming for a Planar Array.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5572, doi. 10.1007/s00034-021-01733-6
- By:
- Publication type:
- Article
16
A 27-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5553, doi. 10.1007/s00034-021-01732-7
- By:
- Publication type:
- Article
17
Noise Time-Domain Signal Reconstruction of Passenger Head Position Considering Compressed Sensing and Multi-source Data Fusion.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5533, doi. 10.1007/s00034-021-01731-8
- By:
- Publication type:
- Article
18
Design of an Improved Low-Power and High-Speed Booth Multiplier.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5500, doi. 10.1007/s00034-021-01730-9
- By:
- Publication type:
- Article
19
Spline Graph Filter Bank with Spectral Sampling.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5744, doi. 10.1007/s00034-021-01729-2
- By:
- Publication type:
- Article
20
Determining the Number of Sources with Diagonal Unloading in Single-Channel Mixtures.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5483, doi. 10.1007/s00034-021-01728-3
- By:
- Publication type:
- Article
21
Adaptive Graph Filtering with Intra-Patch Pixel Smoothing for Image Denoising.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5381, doi. 10.1007/s00034-021-01720-x
- By:
- Publication type:
- Article
22
Efficient Designs of Reversible Synchronous Counters in Nanoscale.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5367, doi. 10.1007/s00034-021-01719-4
- By:
- Publication type:
- Article
23
Chirp Signal Denoising Based on Convolution Neural Network.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5468, doi. 10.1007/s00034-021-01727-4
- By:
- Publication type:
- Article
24
A Novel High-Performance Hybrid Full Adder for VLSI Circuits.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5718, doi. 10.1007/s00034-021-01725-6
- By:
- Publication type:
- Article
25
Fractals with Optimal Information Dimension.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5733, doi. 10.1007/s00034-021-01726-5
- By:
- Publication type:
- Article
26
Asymptotic Properties of Least Squares Estimators and Sequential Least Squares Estimators of a Chirp-like Signal Model Parameters.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5421, doi. 10.1007/s00034-021-01724-7
- By:
- Publication type:
- Article
27
A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5401, doi. 10.1007/s00034-021-01723-8
- By:
- Publication type:
- Article
28
A 170 MHz to 330 MHz Wideband 90 nm CMOS RC–CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5249, doi. 10.1007/s00034-021-01722-9
- By:
- Publication type:
- Article
29
Constrained Least Mean Square Algorithm with Coefficient Reusing.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5705, doi. 10.1007/s00034-021-01721-w
- By:
- Publication type:
- Article
30
A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5351, doi. 10.1007/s00034-021-01718-5
- By:
- Publication type:
- Article
31
Synchronization of a Riemann–Liouville Fractional Time-Delayed Neural Network with Two Inertial Terms.
- Published in:
- Circuits, Systems & Signal Processing, 2021, v. 40, n. 11, p. 5280, doi. 10.1007/s00034-021-01717-6
- By:
- Publication type:
- Article