Parallel Architecture of Reconfigurable Hardware for Massive Output Active Noise Control.
- Published in:
- Parallel Processing Letters, 2019, v. 29, n. 3, p. N.PAG, doi. 10.1142/S0129626419500142
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- Publication type:
- Article
Works matching IS 01296264 AND DT 2019 AND VI 29 AND IP 3
Results: 5
1
2
Applied On-Chip Machine Learning for Dynamic Resource Control in Multithreaded Processors.
- Published in:
- Parallel Processing Letters, 2019, v. 29, n. 3, p. N.PAG, doi. 10.1142/S0129626419500130
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- Publication type:
- Article
3
The Restricted Edge-Connectivity of Kronecker Product Graphs.
- Published in:
- Parallel Processing Letters, 2019, v. 29, n. 3, p. N.PAG, doi. 10.1142/S0129626419500129
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- Publication type:
- Article
4
A Note of Independent Number and Domination Number of Qn,k,m-Graph.
- Published in:
- Parallel Processing Letters, 2019, v. 29, n. 3, p. N.PAG, doi. 10.1142/S0129626419500117
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- Publication type:
- Article
5
Quantum Fuzzy Game Simulation.
- Published in:
- Parallel Processing Letters, 2019, v. 29, n. 3, p. N.PAG, doi. 10.1142/S0129626419500105
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- Publication type:
- Article