Works matching DE "VHDL (Computer hardware description language)"

Results: 122

Formal semantics analysis for VHDL RTL synthesis.

Published in:

Computer Systems Science & Engineering, 2003, v. 18, n. 6, p. 357

By:

Haifeng Zhou, D.;
Wei Cao;
Zhenghui Lin

Publication type:

Article

Ties that bind [hardware description languages].

Published in:

Electronics Systems & Software, 2006, v. 4, n. 5, p. 8, doi. 10.1049/ess:20060501

By:

Crone, A.

Publication type:

Article

Tune analogue simulations for accuracy and speed.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 16, doi. 10.1049/ess:20060302

By:

Raynaud, P.;
Oudinot, J.

Publication type:

Article

A new face for FPGA design.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 28, doi. 10.1049/ess:20060305

By:

Edwards, C.

Publication type:

Article

Blueprint for logic.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 42, doi. 10.1049/ess:20060308

By:

Sordoillet, J.;
Davey, S.

Publication type:

Article

Decodificador Turbo MAP de varias iteraciones.

Published in:

Ingeniería y Desarrollo, 2006, n. 20, p. 106

By:

Chávez, Richard;
Gamarra, Gabriel;
Pardo, Mauricio

Publication type:

Article

Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology.

Published in:

Natural Computing, 2015, v. 14, n. 4, p. 593, doi. 10.1007/s11047-014-9476-z

By:

Kanasugi, Akinori;
Tsukahara, Akihiko;
Ando, Ki

Publication type:

Article

Project verification and construction of superchip tests at the RTL level.

Published in:

Automation & Remote Control, 2013, v. 74, n. 1, p. 113, doi. 10.1134/S0005117913010104

By:

Zolotorevich, L.

Publication type:

Article

Development of tests for VLSI circuit testability at the upper design levels.

Published in:

Automation & Remote Control, 2010, v. 71, n. 9, p. 1888, doi. 10.1134/S0005117910090110

By:

Zolotorevich, L.;
Il'inkova, A.

Publication type:

Article

Multiple-Fault Tolerant Hardware Structure for Cellular Genetic Algorithm.

Published in:

Journal of Computing & Security, 2016, v. 3, n. 1, p. 27

By:

Ashoorian, Peyman;
Damavandi, Yasser Baleghi

Publication type:

Article

Implementing Quadratic Function with Resource Constraints Using MicroBlaze Soft-Core in Xilinx EDK.

Published in:

IUP Journal of Telecommunications, 2015, v. 7, n. 1, p. 7

By:

Mishra, Ashish;
Kedar, Kunal P.;
Shah, Hardik M.;
Raju, K. S.

Publication type:

Article

FPGA Implementation of EPC Gen-2 Protocol and Its Performance Evaluation.

Published in:

IUP Journal of Telecommunications, 2014, v. 6, n. 1, p. 58

By:

Bag, Joyashree;
Rajanna, K. M.;
Sarkar, Subir Kumar

Publication type:

Article

Design and Implementation of a Network on Chip Using FPGA.

Published in:

Al-Rafadain Engineering Journal, 2013, v. 21, n. 1, p. 91

By:

Jabbar, A. I. A.;
AL Malah, Noor Th.

Publication type:

Article

Development of IEEE-754 to Decimal Conversion of Library Components for Floating Point Arithmetic Logic Unit.

Published in:

International Transactions in Mathematical Sciences & Computer, 2011, v. 4, n. 2, p. 165

By:

Jha, Udai Kumar;
Sharma, Subhash Kumar

Publication type:

Article

VHDL DESIGN FOR A SPEED LIMIT SIGN SEGMENTATION ALGORITHM.

Published in:

IADIS International Journal on Computer Science & Information Systems, 2017, v. 12, n. 2, p. 32

By:

Rouabeh, Hanene;
Abdelmoula, Chokri;
Masmoudi, Mohamed

Publication type:

Article

Cardiac Arrhythmias Detection by Neural Networks: VHDL Modeling and Synthesis on FPGA.

Published in:

International Review of Automatic Control, 2012, v. 5, n. 5, p. 689

By:

Chalabi, Z.;
Chalabi, D.;
Amara, A.;
Berrached, N.

Publication type:

Article

Digital control technologies for improving the power quality of power supplies.

Published in:

Neural Computing & Applications, 2013, v. 22, p. 235, doi. 10.1007/s00521-012-1058-3

By:

Shah, P.;
Saxena, Rakesh;
Chawla, M.

Publication type:

Article

Neural network training based on FPGA with floating point number format and it's performance.

Published in:

Neural Computing & Applications, 2011, v. 20, n. 2, p. 195, doi. 10.1007/s00521-010-0423-3

By:

Çavuşlu, Mehmet;
Karakuzu, Cihan;
Şahin, Suhap;
Yakut, Mehmet

Publication type:

Article

Component Modeling and System Level Simulation of Aircraft Electrical Systems.

Published in:

Engineering Letters, 2016, v. 24, n. 2, p. 178

By:

Xiao Li;
Kher, Sameer;
Shimeng Huang;
Ambalavanar, Vel;
Yang Hu

Publication type:

Article

HIDE+: A Logic Based Hardware Development Environment.

Published in:

Engineering Letters, 2008, v. 16, n. 3, p. 460

By:

BenKrid, AbdSamad;
Benkrid, Khaled

Publication type:

Article

FPGA-Based Farsi Handwritten Digit Recognition System.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2010, v. 11, n. 2, p. 17

By:

Moradi, Marzieh;
Pourmina, Mohammad Ali;
Razzazi, Farbod

Publication type:

Article

A novel design of variable-rate RS encoder for ubiquitous high performance multimedia service in Gbps transmission system.

Published in:

Journal of Supercomputing, 2011, v. 55, n. 2, p. 192, doi. 10.1007/s11227-010-0441-z

By:

Yang Sun Lee;
Sang-Soo Yeo

Publication type:

Article

SEU Fault-Injection in VHDL-Based Processors: A Case Study.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 1, p. 87, doi. 10.1007/s10836-013-5351-6

By:

Mansour, Wassim;
Velazco, Raoul

Publication type:

Article

Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique.

Published in:

Computers (2073-431X), 2021, v. 10, n. 10, p. 125, doi. 10.3390/computers10100125

By:

Kharchenko, Vyacheslav;
Illiashenko, Oleg;
Sklyar, Vladimir

Publication type:

Article

Design of 4 bits Combinational Lock Using VHDL.

Published in:

International Journal of Electrical, Electronics & Computer Systems, 2014, v. 19, n. 2, p. 15

By:

Ogeh, Jenny Ebitonere

Publication type:

Article

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System.

Published in:

Journal of Electrical & Computer Engineering, 2018, p. 1, doi. 10.1155/2018/8024168

By:

Duan, Huimin;
Huang, Hui;
Li, Cuihua

Publication type:

Article

Modeling and Implementation of a Power Estimation Methodology for SystemC.

Published in:

International Journal of Reconfigurable Computing, 2012, p. 1, doi. 10.1155/2012/439727

By:

Kuehnle, Matthias;
Wagner, Andre;
Brito, Alisson V.;
Becker, Juergen

Publication type:

Article

A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos.

Published in:

International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/254730

By:

Corrêa, Marcel M.;
Schoenknecht, Mateus T.;
Dornelles, Robson S.;
Agostini, Luciano V.

Publication type:

Article

vMAGIC--Automatic Code Generation for VHDL.

Published in:

International Journal of Reconfigurable Computing, 2009, p. 1, doi. 10.1155/2009/205149

By:

Pohl, Christopher;
Paiz, Carlos;
Porrmann, Mario

Publication type:

Article

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System.

Published in:

International Journal of Reconfigurable Computing, 2008, p. 1, doi. 10.1155/2008/634306

By:

Raygoza-Panduro, Juan José;
Ortega-Cisneros, Susana;
Rivera, Jorge;
de laMora, Alberto

Publication type:

Article

Teaching hardware description languages to satisfy industry expectations.

Published in:

International Journal of Electrical Engineering Education, 2009, v. 46, n. 3, p. 239, doi. 10.7227/IJEEE.46.3.3

By:

Greenwood, Garrison W.

Publication type:

Article

Instructional tools for designing and analysing a very simple CPU.

Published in:

International Journal of Electrical Engineering Education, 2006, v. 43, n. 3, p. 261, doi. 10.7227/IJEEE.43.3.7

By:

Carpinelli, John D.;
Zaman, Titu

Publication type:

Article

A virtual interactive teaching environment using XML and augmented reality.

Published in:

International Journal of Electrical Engineering Education, 2001, v. 38, n. 4, p. 316, doi. 10.7227/IJEEE.38.4.5

By:

White, Martin;
Jay, Emmanuel;
Liarokapis, Fotis;
Kostakis, Costas;
Lister, Paul

Publication type:

Article

Parallelized and pipelined hardware implementation of computationally expensive prediction filters.

Published in:

Concurrency & Computation: Practice & Experience, 2009, v. 21, n. 18, p. 2478, doi. 10.1002/cpe.1480

By:

Gracia, Luis;
Perez-Vidal, Carlos

Publication type:

Article

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules.

Published in:

Computers, Materials & Continua, 2022, v. 71, n. 3, p. 4319, doi. 10.32604/cmc.2022.022988

By:

Alanazi, Turki M.;
Atitallah, Ahmed Ben

Publication type:

Article

A case study of varying the EEG localization error using different electrode configurations: Embedded solution.

Published in:

Journal of Information Assurance & Security, 2016, v. 11, n. 5, p. 242

By:

Khemakhem, Rafik;
Frikha, Tarek;
Hadriche, Abir;
Diguet, Jean-Philippe

Publication type:

Article

A New Efficient Symmetric Encryption Algorithm Design and Implementation.

Published in:

Journal of Information Assurance & Security, 2012, v. 7, n. 2, p. 102

By:

Tawalbeh, Lo'ai;
Al-Hajsalem, Hend;
Abu-Qtaish, Tasneem;
Khatatbeh, Ayat

Publication type:

Article

Analysis for Design and Transformation of Autosynchronous State Machines.

Published in:

Radioengineering, 2010, v. 19, n. 1, p. 99

By:

Kováč, Michal;
Kolouch, Jaromír

Publication type:

Article

Fast Processing of Non-Repeated Values in Hardware.

Published in:

Electronics & Electrical Engineering, 2017, v. 23, n. 3, p. 74, doi. 10.5755/j01.eie.23.3.18336

By:

Skliarova, Iouliia;
Sklyarov, Valery;
Sudnitson, Alexander

Publication type:

Article

Software tool for efficient FPGA design of direct data domain approach for space-time adaptive processing.

Published in:

Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 13, p. 1, doi. 10.1049/el.2013.1307

By:

Jarrah, A.;
Jamali, M.

Publication type:

Article

Synthesis and implementation of the ordered access memory in programmable logic devices.

Published in:

Metallurgical & Mining Industry, 2016, n. 4, p. 58

By:

Lishchyna, Nataliia;
Lishchyna, Valerii;
Herasymchuk, Oleh;
Yashchuk, Andrii

Publication type:

Article

CONSTRUÇÃO DE UM BRAÇO ROBÓTICO CONTROLADO A PARTIR DE UM FPGA.

Published in:

Colloquium Exactarum, 2012, v. 4, n. 1, p. 1, doi. 10.5747/ce.2012.v04.n1.e040

By:

Mimoso Souza, Geovane;
Torres Delgado, Martha Ximena;
Xavier Cruz, Tiago

Publication type:

Article

A Serial Processing FIR Inverse Filter Circuit.

Published in:

Electronics & Communications in Japan, 2015, v. 98, n. 12, p. 37, doi. 10.1002/ecj.11761

By:

TAKATO, KENJI

Publication type:

Article

Circuit Design Education by Introducing Circuit Diagram-Based CPU Design.

Published in:

Electronics & Communications in Japan, 2015, v. 98, n. 12, p. 46, doi. 10.1002/ecj.11764

By:

OHMURA, MICHIROH;
TANAKA, TAKESHI

Publication type:

Article

Performance Evaluation of Squaring Operation by Vedic Mathematics.

Published in:

IETE Journal of Research, 2011, v. 57, n. 1, p. 39, doi. 10.4103/0377-2063.78327

By:

Kasliwal, Prabha S.;
Patil, B. P.;
Gautam, D. K.

Publication type:

Article

A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs.

Published in:

Journal of Circuits, Systems & Computers, 2019, v. 28, n. 3, p. N.PAG, doi. 10.1142/S0218126619500543

By:

Khalifa, Khaled Ben;
Bedoui, Mohamed Hédi

Publication type:

Article

A Complete Embedded System Design of Breakout Game.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 12, p. -1, doi. 10.1142/S0218126617501882

By:

Tural-Polat, Sadiye Nergis

Publication type:

Article

A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System.

Published in:

Journal of Circuits, Systems & Computers, 2017, v. 26, n. 1, p. 1, doi. 10.1142/S0218126617500153

By:

Koyuncu, İsmail;
Şahin, İbrahim;
Gloster, Clay;
Sarıtekin, Namık Kemal

Publication type:

Article

Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet).

Published in:

Journal of Circuits, Systems & Computers, 2016, v. 25, n. 3, p. -1, doi. 10.1142/S0218126616400120

By:

Urban, Roberto;
Vierhaus, Heinrich T.;
Schölzel, Mario;
Altmann, Enrico;
Seelig, Horst

Publication type:

Article

Simultaneous Multithreaded Matrix Processor.

Published in:

Journal of Circuits, Systems & Computers, 2015, v. 24, n. 8, p. -1, doi. 10.1142/S0218126615501145

By:

Soliman, Mostafa I.;
Elsayed, Elsayed A.

Publication type:

Article