Works matching DE "VHDL (Computer hardware description language)"
Results: 121
Performance evaluation of a new efficient H.264 intraprediction scheme.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 3, p. 1967, doi. 10.3906/elk-1312-250
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IMAGE CONTOUR SEGMENTATION IN HARDWARE.
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- Radio Electronics, Computer Science, Control, 2015, v. 4, p. 66, doi. 10.15588/1607-3274-2015-4-10
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- Article
A Reconfigurable Hybrid Architecture for HomePNA3.1/Ethernet MAC.
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- Majlesi Journal of Electrical Engineering, 2011, v. 5, n. 4, p. 46
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A case study of varying the EEG localization error using different electrode configurations: Embedded solution.
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- Journal of Information Assurance & Security, 2016, v. 11, n. 5, p. 242
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A New Efficient Symmetric Encryption Algorithm Design and Implementation.
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- Journal of Information Assurance & Security, 2012, v. 7, n. 2, p. 102
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Improved Data Preprocessing Algorithm for Time-Domain Induced Polarization Method with Digital Notch Filter.
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- Acta Geophysica, 2016, v. 64, n. 6, p. 2264, doi. 10.1515/acgeo-2016-0015
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- Article
Efficient Hardware Implementations for Tripling Oriented Elliptic Curve Crypto-System.
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- International Review on Computers & Software, 2014, v. 9, n. 4, p. 609
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- Article
Advanced Modulating Techniques for Multilevel Inverters by Using FPGA.
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- International Review of Electrical Engineering, 2010, v. 5, n. 3, p. 842
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Suspended gate field effect transistor type microelectromechanical systems resonators modelling with micro-Raman spectroscopy measured residual stress.
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- Micro & Nano Letters (Wiley-Blackwell), 2013, v. 8, n. 10, p. 614, doi. 10.1049/mnl.2013.0272
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- Article
DESIGN AND SIMULATION OF SINGLE-PRECISION INEXACT FLOATING-POINT ADDER/SUBTRACTOR.
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- i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 4, p. 7, doi. 10.26634/jele.6.4.8087
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- Article
DESIGN AND ANALYSIS OF 32X32 BIT ALU USING HIGH-SPEED VEDIC-WALLACE MULTIPLIER BASED ON VEDIC MATHEMATICS.
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- i-Manager's Journal on Electronics Engineering, 2016, v. 6, n. 3, p. 7, doi. 10.26634/jele.6.3.5954
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AN EFFICIENT ARCHITECTURE FOR SINGLE PRECISION FLOATING POINT MULTIPLIER USING VARIOUS ALGORITHMS.
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- i-Manager's Journal on Electronics Engineering, 2015, v. 5, n. 3, p. 11, doi. 10.26634/jele.5.3.3393
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Microprocessor design using hardware description language.
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- European Journal of Engineering Education, 2008, v. 33, n. 4, p. 425, doi. 10.1080/03043790802253384
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- Article
Implementación del algoritmo Threefish-256 en hardware reconfigurable.
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- Iteckne, 2014, v. 11, n. 2, p. 149, doi. 10.15332/iteckne.v11i2.725
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- Article
Relating Event and Trace Semantics of Hardware Description Languages.
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- Computer Journal, 2002, v. 45, n. 1, p. 27, doi. 10.1093/comjnl/45.1.27
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- Article
Property-Model Methodology: A Model-Based Systems Engineering Approach Using VHDL-AMS.
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- Systems Engineering, 2014, v. 17, n. 3, p. 249, doi. 10.1002/sys.21267
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- Article
Development of IEEE-754 to Decimal Conversion of Library Components for Floating Point Arithmetic Logic Unit.
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- International Transactions in Mathematical Sciences & Computer, 2011, v. 4, n. 2, p. 165
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Modeling and Implementation of a Power Estimation Methodology for SystemC.
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- International Journal of Reconfigurable Computing, 2012, p. 1, doi. 10.1155/2012/439727
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A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos.
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- International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/254730
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- Article
vMAGIC--Automatic Code Generation for VHDL.
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- International Journal of Reconfigurable Computing, 2009, p. 1, doi. 10.1155/2009/205149
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- Article
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System.
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- International Journal of Reconfigurable Computing, 2008, p. 1, doi. 10.1155/2008/634306
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- Article
Analysis for Design and Transformation of Autosynchronous State Machines.
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- Radioengineering, 2010, v. 19, n. 1, p. 99
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Teaching hardware description languages to satisfy industry expectations.
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- International Journal of Electrical Engineering Education, 2009, v. 46, n. 3, p. 239, doi. 10.7227/IJEEE.46.3.3
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- Article
Instructional tools for designing and analysing a very simple CPU.
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- International Journal of Electrical Engineering Education, 2006, v. 43, n. 3, p. 261, doi. 10.7227/IJEEE.43.3.7
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- Article
A virtual interactive teaching environment using XML and augmented reality.
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- International Journal of Electrical Engineering Education, 2001, v. 38, n. 4, p. 316, doi. 10.7227/IJEEE.38.4.5
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- Article
Fast Processing of Non-Repeated Values in Hardware.
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- Electronics & Electrical Engineering, 2017, v. 23, n. 3, p. 74, doi. 10.5755/j01.eie.23.3.18336
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- Article
VHDL Optimized Model of a Multiplier in Finite Fields.
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- Ingeniería y Universidad, 2017, v. 21, n. 2, p. 45, doi. 10.11144/Javeriana.iyu21-2.vhdl
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- Article
Codificador RS(255,k) en hardware reconfigurable orientado a radio cognitivo.
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- Ingeniería y Universidad, 2013, v. 17, n. 1, p. 77
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- Article
CODIFICADOR Y DECODIFICADOR DIGITAL REED-SOLOMON PROGRAMADOS PARA HARDWARE RECONFIGURABLE.
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- Ingeniería y Universidad, 2007, v. 11, n. 1, p. 17
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- Article
FPGA-Based Farsi Handwritten Digit Recognition System.
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- International Journal of Simulation: Systems, Science & Technology, 2010, v. 11, n. 2, p. 17
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Decodificador Turbo MAP de varias iteraciones.
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- Ingeniería y Desarrollo, 2006, n. 20, p. 106
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Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology.
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- Natural Computing, 2015, v. 14, n. 4, p. 593, doi. 10.1007/s11047-014-9476-z
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- Article
A Synthesizable VHDL Model of the Exact Solution for Three-dimensional Hyperbolic Positioning System.
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- VLSI Design, 2002, v. 15, n. 2, p. 507, doi. 10.1080/1065514021000012129
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- Article
Design Procedure Based on VHDL Language Transformations.
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- VLSI Design, 2002, v. 14, n. 4, p. 349, doi. 10.1080/10655140290011159
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- Article
Algorithm & Design of an Efficient Floating Point ADD/SUB Unit for an Experimental CPU.
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- International Journal of Intelligent Information Technology Application, 2009, v. 2, n. 6, p. 273
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- Article
Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net.
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- Journal of Integrated Circuits & Systems, 2016, v. 11, n. 2, p. 75, doi. 10.29292/jics.v11i2.432
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- Article
Quantitative comparison of performance analysis techniques for modular and generic network-on-chip.
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- Advances in Radio Science, 2009, v. 7, p. 107, doi. 10.5194/ars-7-107-2009
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- Article
Highly Parallel Modular Multiplier for Elliptic Curve Cryptography in Residue Number System.
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- Circuits, Systems & Signal Processing, 2017, v. 36, n. 3, p. 1027, doi. 10.1007/s00034-016-0336-1
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- Article
Computer Architecture and FPGAs: A Learning-by-Doing Methodology for Digital-Native Students.
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- Computer Applications in Engineering Education, 2015, v. 23, n. 3, p. 464, doi. 10.1002/cae.21617
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- Article
E-assessment of Matlab assignments in Moodle: Application to an introductory programming course for engineers.
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- Computer Applications in Engineering Education, 2013, v. 21, n. 4, p. 728, doi. 10.1002/cae.20520
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- Article
FPGA-Matlab-based open core for three-time controllers in automatic control applications.
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- Computer Applications in Engineering Education, 2013, v. 21, p. E132, doi. 10.1002/cae.20526
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- Article
An FPGA-based integrated environment for computer architecture.
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- Computer Applications in Engineering Education, 2013, v. 21, n. 1, p. 26, doi. 10.1002/cae.20448
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- Article
A Review on FPGA Implementation of Distributed Canny Edge Detector.
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- Grenze International Journal of Engineering & Technology (GIJET), 2017, v. 3, n. 3, p. 94
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- Article
Integrated classifier simulator and neurochip VHDL implementation.
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- International Journal of Computer Mathematics, 2003, v. 80, n. 11, p. 1343, doi. 10.1080/0020716031000148223
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- Article
Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2021, v. 11, n. 5, p. 3844, doi. 10.11591/ijece.v11i5.pp3844-3854
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- Article
VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2017, v. 7, n. 4, p. 1824, doi. 10.11591/ijece.v7i4.pp1824-1832
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- Article
FPGA Based Control Method for Three Phase BLDC Motor.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 4, p. 1434, doi. 10.11591/ijece.v6i4.10103
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- Article
Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 6, p. 805, doi. 10.11591/ijece.v3i6.4185
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- Article
A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 4, p. 524, doi. 10.11591/ijece.v3i4.3173
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- Article
Simulating the effects of logic faults in implementation-level VITAL-compliant models.
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- Computing, 2019, v. 101, n. 2, p. 77, doi. 10.1007/s00607-018-0651-4
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- Article