Works matching DE "VERY large scale circuit integration"

Results: 858

An efficient algorithm and architecture for the VLSI implementation of type IV DST using short quasi-band correlation structures allowing efficient incorporation of techniques used for hardware security.

Published in:

Journal of Engineering Sciences & Innovation (JESI), 2024, v. 9, n. 3, p. 343, doi. 10.56958/jesi.2024.9.3.343

By:

COTOROBAI, LAURA TEODORA;
CHIPER, DORU FLORIN

Publication type:

Article

A Method for Synthesizing Ultra-Large-Scale Clock Trees.

Published in:

Algorithms, 2025, v. 18, n. 5, p. 249, doi. 10.3390/a18050249

By:

Li, Ziheng;
Chen, Benyuan;
Wang, Wanting;
Lv, Hui;
Lv, Qinghua;
Chen, Jie;
Wang, Yan;
Li, Juan;
Zhang, Cheng

Publication type:

Article

Future scaling must address within-device gate oxide variation.

Published in:

Solid State Technology, 1999, v. 42, n. 8, p. 26

By:

Burggraaf, Pieter

Publication type:

Article

Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications.

Published in:

Journal of Electronic Materials, 2024, v. 53, n. 7, p. 3626, doi. 10.1007/s11664-024-11125-6

By:

Hussain, Syed Ali;
Prasad V, P N S B S V;
Sanki, Pradyut Kumar

Publication type:

Article

Hot spots on an interconnection network for broadcast communication.

Published in:

Computer Systems Science & Engineering, 2004, v. 19, n. 1, p. 49

By:

Katsinis, C.

Publication type:

Article

Fast and efficient allocation for mesh systems.

Published in:

Computer Systems Science & Engineering, 2003, v. 18, n. 3, p. 161

By:

Lin-Chih Chen;
Da-Ren Chen;
Chiun-Chieh Hsu;
Hon-Ren Lin

Publication type:

Article

Impact of tunneling conductance on the performance of multi walled carbon nanotubes as VLSI interconnects for nano-scaled technology nodes.

Published in:

Journal of Materials Science: Materials in Electronics, 2017, v. 28, n. 6, p. 4818, doi. 10.1007/s10854-016-6128-3

By:

Litoria, Prakhar;
Sandha, Karmjit;
Kansal, Ankush

Publication type:

Article

Crystallization processes of SrTiO films prepared by PVP-modified sol-gel method.

Published in:

Journal of Materials Science: Materials in Electronics, 2017, v. 28, n. 1, p. 944, doi. 10.1007/s10854-016-5612-0

By:

Peng, Yong;
Yao, Manwen;
Xiao, Ruihua;
Li, Fei;
Yao, Xi

Publication type:

Article

A survey paper on design and implementation of multipliers for digital system applications.

Published in:

Artificial Intelligence Review, 2022, v. 55, n. 6, p. 4575, doi. 10.1007/s10462-021-10113-0

By:

Immareddy, Srikanth;
Sundaramoorthy, Aunmetha

Publication type:

Article

EFFICIENT CHARACTERIZATION OF MULTILEVEL INTERCONNECTIONS ON THE GaAs-BASED VLSICs.

Published in:

Microwave & Optical Technology Letters, 1988, v. 1, n. 7, p. 252, doi. 10.1002/mop.4650010709

By:

Goel, A. K.;
Huang, Y. R.

Publication type:

Article

VLSI Architecture for Implementing OTFS.

Published in:

Wireless Personal Communications, 2024, v. 137, n. 3, p. 1931, doi. 10.1007/s11277-024-11488-3

By:

Shadangi, Ashish Ranjan;
Das, Suvra Sekhar;
Chakrabarti, Indrajit

Publication type:

Article

Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits.

Published in:

Automation & Remote Control, 2015, v. 76, n. 4, p. 658, doi. 10.1134/S0005117915040104

By:

Matrosova, A.;
Lipskii, V.

Publication type:

Article

Development of tests for VLSI circuit testability at the upper design levels.

Published in:

Automation & Remote Control, 2010, v. 71, n. 9, p. 1888, doi. 10.1134/S0005117910090110

By:

Zolotorevich, L.;
Il'inkova, A.

Publication type:

Article

Analog-to-digital interfaces for microcontroller-based adaptive cyclic regulating devices for electrical plants.

Published in:

Automation & Remote Control, 2006, v. 67, n. 5, p. 824, doi. 10.1134/S0005117906050146

By:

Krutchinskii, S.

Publication type:

Article

Malyugin's Theorems: A New Concept in Logical Control, VLSI Design, and Data Structures for New Technologies.

Published in:

Automation & Remote Control, 2004, v. 65, n. 6, p. 893, doi. 10.1023/B:AURC.0000030902.91316.b9

By:

Shmerko, V. P.

Publication type:

Article

IMPLEMENTATION OF APPROXIMATE ADDERS AND MULTIPLIERS FOR ERROR TOLERANT IMAGE PROCESSING.

Published in:

i-Manager's Journal on Image Processing, 2021, v. 8, n. 3, p. 21, doi. 10.26634/jip.8.3.18218

By:

MANI, P.;
PRIYADHARSHINI, S.;
PRIYANGA, N.;
RESHMA, V.

Publication type:

Article

VLSI Structures for DNA Sequencing--A Survey.

Published in:

Bioengineering (Basel), 2020, v. 7, n. 2, p. 1, doi. 10.3390/bioengineering7020049

By:

Islam, Mohammad A.;
Datta, Palash K.;
Myler, Harley

Publication type:

Article

Comprehensive Study on High Purity Semiconducting Carbon Nanotube Extraction.

Published in:

Advanced Electronic Materials, 2022, v. 8, n. 9, p. 1, doi. 10.1002/aelm.202101377

By:

Srimani, Tathagata;
Ding, Jianfu;
Yu, Andrew;
Kanhaiya, Pritpal;
Lau, Christian;
Ho, Rebecca;
Humes, Jefford;
Kingston, Christopher T.;
Malenfant, Patrick R.L.;
Shulaker, Max M.

Publication type:

Article

Exploring Nonuniform Structure of NSRTDs for Characterizing MACA Rules in the Null-Boundary Condition.

Published in:

Complex Systems, 2025, v. 34, n. 1, p. 91, doi. 10.25088/ComplexSystems.34.1.91

By:

Hazra, Suvadip;
Banerjee, Som;
Dalui, Mamata;
Chakraborty, Bidesh

Publication type:

Article

A Generic NSRTD Framework for Characterizing Cellular Automaton Rules in Constant (0/1) Boundary Conditions.

Published in:

Complex Systems, 2024, v. 33, n. 1, p. 61, doi. 10.25088/complexsystems.33.1.61

By:

Banerjee, Som;
Dalui, Mamata;
Hazra, Suvadip

Publication type:

Article

Characterization of Single Length Cycle Two-Attractor Cellular Automata Using Next-State Rule Minterm Transition Diagram.

Published in:

Complex Systems, 2022, v. 31, n. 4, p. 363, doi. 10.25088/ComplexSystems.31.4.363

By:

Hazra, Suvadip;
Dalui, Mamata

Publication type:

Article

Optimized design and performance analysis of novel comparator and full adder in nanoscale.

Published in:

Cogent Engineering, 2016, v. 3, n. 1, p. N.PAG, doi. 10.1080/23311916.2016.1237864

By:

Abdullah-Al-Shafi, Md.;
Bahar, Ali Newaz;
Ai, Qingsong

Publication type:

Article

A discrete dynamic convexized method for VLSI circuit partitioning.

Published in:

Optimization Methods & Software, 2013, v. 28, n. 4, p. 670, doi. 10.1080/10556788.2012.663372

By:

Chen, Jiarui;
Zhu, Wenxing

Publication type:

Article

A survey on pristine and intercalation doped graphene nanoribbon interconnect for future VLSI circuits.

Published in:

AIMS Materials Science, 2021, v. 8, n. 2, p. 247, doi. 10.3934/matersci.2021016

By:

Das, Subhajit;
Bhattacharya, Sandip;
Das, Debaprasad;
Rahaman, Hafizur

Publication type:

Article

Enhanced Low-Power Digital Signal Processing via a Novel Reversible MCML-Based Carry Select Adder.

Published in:

Traitement du Signal, 2024, v. 41, n. 2, p. 1043, doi. 10.18280/ts.410245

By:

Shanmugam, Sharmila Devi

Publication type:

Article

Efficient Power Estimation Using DSENT for 3D-Mesh on Chip Optic Communication Network.

Published in:

Ingénierie des Systèmes d'Information, 2024, v. 29, n. 1, p. 27, doi. 10.18280/isi.290104

By:

Ahmed, Mushtaq;
Ambudkar, Bhavna;
Yadav, Akash

Publication type:

Article

Summarization of Intra/Inter Chip Wireless Interconnection Technology.

Published in:

Telecommunication Engineering, 2014, v. 54, n. 7, p. 1031, doi. 10.3969/j.issn.1001-893x.2014.07.030

By:

WANG Yi-wen;
LI Xue-hua

Publication type:

Article

A PSO based optimal repeater insertion technique for carbon nanotube interconnects.

Published in:

International Journal of Electronics Letters, 2022, v. 10, n. 3, p. 344, doi. 10.1080/21681724.2021.1941283

By:

Uma Sathyakam, P.;
Raj, Shubham;
Karthikeyan, A.;
Mallick, P. S.

Publication type:

Article

A Thermal Model for Carbon Nanotube Interconnects.

Published in:

Nanomaterials (2079-4991), 2013, v. 3, n. 2, p. 229, doi. 10.3390/nano3020229

By:

Mohsin, Kaji Muhammad;
Ashok Srivastava;
Sharma, Ashwani K.;
Mayberry, Clay

Publication type:

Article

Pin density technique for congestion estimation and reduction of optimized design during placement and routing.

Published in:

Applied Nanoscience, 2023, v. 13, n. 3, p. 1819, doi. 10.1007/s13204-021-02173-z

By:

Karimullah, Shaik;
Vishnuvardhan, D.

Publication type:

Article

Fuzzy Linear Fractional Set Covering Problem with Imprecise Costs.

Published in:

RAIRO -- Operations Research, 2014, v. 48, n. 3, p. 415, doi. 10.1051/ro/2014015

By:

Gupta, Rashmi;
Saxena, Ratnesh Rajan

Publication type:

Article

Design and Implementation of Crosstalk Avoidance Using Bit-Stuffing Algorithms in VLSI Circuits.

Published in:

IUP Journal of Telecommunications, 2018, v. 10, n. 1, p. 33

By:

Jyothi, B.;
Obulesu, B.

Publication type:

Article

A LITERATURE SURVEY ON FIR DIGITAL FILTERS.

Published in:

Annals of the Faculty of Engineering Hunedoara - International Journal of Engineering, 2021, n. 1, p. 37

By:

KARTHIK, Anjanappa;
MALAVIKAA, Madhusudhan;
MANOJ, Sridhar Koundinya

Publication type:

Article

A Methodology to Distribute On-Chip Voltage Regulators to Improve the Security of Hardware Masking.

Published in:

Information (2078-2489), 2024, v. 15, n. 8, p. 488, doi. 10.3390/info15080488

By:

Seçkiner, Soner;
Köse, Selçuk

Publication type:

Article

Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios.

Published in:

Information (2078-2489), 2022, v. 13, n. 5, p. 212, doi. 10.3390/info13050212

By:

Dadaliaris, Antonios;
Kranas, George;
Oikonomou, Panagiotis;
Floros, George;
Dossis, Michael

Publication type:

Article

A Substrate Current Less Control Method for CMOS Integration of Power Bridges.

Published in:

Advances in Power Electronics, 2010, p. 1, doi. 10.1155/2010/909612

By:

Krupar, Joerg;
Hauswald, Heiko;
Naumann, Ronny

Publication type:

Article

VLSI PLATFORM FOR REAL-WORLD INTELLIGENT INTEGRATED SYSTEMS BASED ON ALGORITHM SELECTION.

Published in:

IADIS International Journal on Computer Science & Information Systems, 2013, v. 8, n. 2, p. 72

By:

Lukac, Martin;
Michitaka Kameyama;
Yoshichika Fujioka

Publication type:

Article

Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications.

Published in:

Australian Journal of Electrical & Electronic Engineering, 2018, v. 15, n. 1/2, p. 9, doi. 10.1080/1448837X.2018.1480305

By:

Walunj, Rupali Ashok;
Pable, Sachin Dattatray;
Kharate, Gajanan Kashiram

Publication type:

Article

An efficient digital gammatone filter architecture for Cochlear implant.

Published in:

Australian Journal of Electrical & Electronic Engineering, 2013, v. 10, n. 2, p. 217, doi. 10.7158/E11-107.2013.10.2

By:

Rajalakshmi, K.;
Kandaswamy, A.;
Subhathradevi, N.

Publication type:

Article

Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system.

Published in:

Australian Journal of Electrical & Electronic Engineering, 2010, v. 7, n. 1, p. 73, doi. 10.1080/1448837X.2010.11464259

By:

Islam, S. Z.;
Ali, M. A. M.

Publication type:

Article

A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application.

Published in:

Journal of Nanotechnology, 2018, p. 1, doi. 10.1155/2018/2934268

By:

Singar, Sumitra;
Joshi, N. K.;
Ghosh, P. K.

Publication type:

Article

A discovery of an ultra-pure water detection method based on water mark.

Published in:

Modern Physics Letters B, 2015, v. 29, n. 3, p. -1, doi. 10.1142/S0217984914502716

By:

Cao, Hui-Wen;
Jing, Yu-Peng;
Zhao, Shi-Rui;
Xu, Xin-Wei;
Tian, He;
Xin, Xin;
Li, Xiao-Ning;
Liu, Bo;
Liu, Rui-Tao;
Wang, Gang;
Ge, Jie;
Cai, Hua-Lin;
Yang, Yi;
Ren, Tian-Ling

Publication type:

Article

Hybrid Architecture of Genetic Algorithm and Simulated Annealing.

Published in:

Engineering Letters, 2008, v. 16, n. 3, p. 339

By:

Yoshikawa, Masaya;
Yamauchi, Hironori;
Terai, Hidekazu

Publication type:

Article

Very large-scale arrays of biomolecules.

Published in:

1999

By:

Montgomery, Don

Publication type:

Abstract

Spintronics: from Basic Research to VLSI Application.

Published in:

AAPPS Bulletin, 2015, v. 25, n. 1, p. 4

By:

KANAI, S.;
MATSUKURA, F.;
IKEDA, S.;
SATO, H.;
FUKAMI, S.;
OHNO, H.

Publication type:

Article

A FPGA-Based Systolic Array Prototype Implementing the Quadrant Interlocking Factorization Method.

Published in:

Journal of Supercomputing, 2006, v. 37, n. 3, p. 319, doi. 10.1007/s11227-006-6633-x

By:

Karra, M.;
Bekakos, M.

Publication type:

Article

Implementation of the SHA-2 Hash Family Standard Using FPGAs.

Published in:

Journal of Supercomputing, 2005, v. 31, n. 3, p. 227, doi. 10.1007/s11227-005-0086-5

By:

Sklavos, N.;
Koufopavlou, O.

Publication type:

Article

Dynamic Functional Unit Assignment for Low Power.

Published in:

Journal of Supercomputing, 2005, v. 31, n. 1, p. 47, doi. 10.1023/B:SUPE.0000049324.79531.a9

By:

Haga, Steve;
Reeves, Natasha;
Barua, Rajeev;
Marculescu, Diana

Publication type:

Article

Editorial.

Published in:

2019

By:

Agrawal, Vishwani D.

Publication type:

Editorial

Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations.

Published in:

Journal of Electronic Testing, 2019, v. 35, n. 6, p. 779, doi. 10.1007/s10836-019-05840-w

By:

Palchaudhuri, Ayan;
Dhar, Anindya Sundar

Publication type:

Article