Works matching DE "VERILOG (Computer hardware description language)"

Results: 133

A new face for FPGA design.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 28, doi. 10.1049/ess:20060305

By:

Edwards, C.

Publication type:

Article

Blueprint for logic.

Published in:

Electronics Systems & Software, 2006, v. 4, n. 3, p. 42, doi. 10.1049/ess:20060308

By:

Sordoillet, J.;
Davey, S.

Publication type:

Article

HDL Constructs in Linear Word-Level Decision Diagram Based Specification.

Published in:

Automation & Remote Control, 2004, v. 65, n. 6, p. 913, doi. 10.1023/B:AURC.0000030903.92620.b1

By:

Wahid, K.;
Lu, D. C.;
Rahman, C.

Publication type:

Article

A Comprehensive Analog–Mixed Signal (AMS) Simulations Environment.

Published in:

Chips, 2024, v. 3, n. 3, p. 258, doi. 10.3390/chips3030013

By:

Castaldo, Enrico;
Gibilaro, Marco Eugenio

Publication type:

Article

基于FPGA的双三相永磁同步电机伺服控制系统.

Published in:

Electronic Science & Technology, 2022, v. 35, n. 12, p. 49, doi. 10.16180/j.cnki.issn1007-7820.2022.12.007

By:

袁庆庆;
胡旭;
刘志勇;
马婷;
蒋全

Publication type:

Article

基于 Qt 的 Veribg 故障注入工具设计与实现.

Published in:

Experimental Technology & Management, 2019, v. 36, n. 1, p. 153, doi. 10.16791/j.cnki.sjg.2019.01.036

By:

王洁;
康俊杰;
HOU Gang;
于健海

Publication type:

Article

ineuralFPGA: Implementation of an Optimized DNN Model for Real-Time Applications.

Published in:

Ingénierie des Systèmes d'Information, 2025, v. 30, n. 4, p. 1101, doi. 10.18280/isi.300425

By:

Jain, Vineet;
Sharma, Abhishek;
Jain, Prateek;
Bezerra, Augusto;
Sharma, Sunil;
Alasmari, Sultan

Publication type:

Article

P.19: Density-of-States Based Device-Circuit Co-Design Platform for Solution-Processed Organic Integrated Circuits.

Published in:

2013

By:

Jang, Jaeman;
Kim, Jaehyeong;
Lee, Jaewook;
Jo, Chunhyung;
Jun, Sungwoo;
Kim, Hyeongjung;
Choi, Sunwoong;
Kim, Dong Myong;
Lee, Jiyoul;
Koo, Bonwon;
Chung, Jong Won;
Kim, Dae Hwan

Publication type:

Other

Implementation of Crosstalk Avoidance and Low Power Coding Scheme for SoC.

Published in:

IUP Journal of Telecommunications, 2018, v. 10, n. 1, p. 50

By:

Chakradhar, D.;
Obulesu, B.

Publication type:

Article

Profiling Techniques in QuestaSim and Design of a Profiler Hardware Module.

Published in:

IUP Journal of Telecommunications, 2017, v. 9, n. 1, p. 54

By:

Mishra, Ashish;
B., Suhas;
Kumar, Suresh

Publication type:

Article

Massively Parallel Combinational Binary Neural Networks for Edge Processing.

Published in:

Electrotechnical Review / Elektrotehniski Vestnik, 2019, v. 86, n. 1/2, p. 47

By:

Murovič, Tadej;
Trost, Andrej

Publication type:

Article

Large-Signal DG-MOSFET Modelling for RFID Rectification.

Published in:

Advances in Condensed Matter Physics, 2016, p. 1, doi. 10.1155/2016/8017139

By:

Rodríguez, R.;
González, B.;
García, J.;
Lázaro, A.;
Iñiguez, B.;
Hernández, A.

Publication type:

Article

An ASIC Architecture for Generating Optimum Mixed Polarity Reed-Muller Expression.

Published in:

Engineering Letters, 2006, v. 13, n. 4, p. 236

By:

Khan, Mozammel H. A.

Publication type:

Article

Verilog HDL Simulator Technology: A Survey.

Published in:

Journal of Electronic Testing, 2014, v. 30, n. 3, p. 255, doi. 10.1007/s10836-014-5449-5

By:

Tan, Tze;
Rosdi, Bakhtiar

Publication type:

Article

Editorial.

Published in:

2014

By:

Agrawal, Vishwani

Publication type:

Editorial

SV DPI技术在FPGA仿真验证的应用探讨.

Published in:

Computer Measurement & Control, 2018, v. 26, n. 6, p. 264, doi. 10.16526/j.cnki.11-4762/tp.2018.06.067

By:

祝周荣;
关俊强;
李前进;
赵超;
刘芳汝

Publication type:

Article

基于FPGA 的 RC4 加密算法设计及实现.

Published in:

Computer Measurement & Control, 2018, v. 26, n. 2, p. 252, doi. 10.16526/j.cnki.11-4762/tp.2018.02.062

By:

苗三立;
左金印;
宋宇飞

Publication type:

Article

General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors.

Published in:

Journal of Information & Communication Convergence Engineering, 2016, v. 14, n. 2, p. 115, doi. 10.6109/jicce.2016.14.2.115

By:

Najam, Syed Faraz;
Michael Loong Peng Tan;
Yun Seop Yu

Publication type:

Article

Expanding the UVM Register Model towards Automation and Simplicity of Use.

Published in:

International Journal of Advanced Research in Computer Science, 2017, v. 8, n. 3, p. 471

By:

Jain, Abhishek;
Gupta, Richa

Publication type:

Article

J1 Accumulator-Based Processor for Educational Purposes.

Published in:

International Journal of Advanced Research in Computer Science, 2013, v. 4, n. 2, p. 191

By:

Mansour, Askari Yadollahpour;
Navin, Ahmad Habibizad;
Rahmani, Amir Masoud

Publication type:

Article

AUTOMATED DEBUGGING OF VERILOG DESIGNS.

Published in:

International Journal of Software Engineering & Knowledge Engineering, 2012, v. 22, n. 5, p. 695, doi. 10.1142/S0218194012500209

By:

PEISCHL, BERNHARD;
RIAZ, NAVEED;
WOTAWA, FRANZ

Publication type:

Article

Teaching hardware description languages to satisfy industry expectations.

Published in:

International Journal of Electrical Engineering Education, 2009, v. 46, n. 3, p. 239, doi. 10.7227/IJEEE.46.3.3

By:

Greenwood, Garrison W.

Publication type:

Article

Circuit realization and FPGA-based implementation of a fractional-order chaotic system for cancellable face recognition.

Published in:

Multimedia Tools & Applications, 2024, v. 83, n. 34, p. 81565, doi. 10.1007/s11042-023-15867-z

By:

Badr, Iman S.;
Radwan, Ahmed G.;
EL-Rabaie, El-Sayed M.;
Said, Lobna A.;
El-Shafai, Walid;
El-Banby, Ghada M.;
Abd El-Samie, Fathi E.

Publication type:

Article

Content addressable memory (CAM) based robust anonymous authentication and integrity preservation scheme for wireless body area networks (WBAN).

Published in:

Multimedia Tools & Applications, 2024, v. 83, n. 7, p. 20429, doi. 10.1007/s11042-023-16257-1

By:

Rajasekaran, Arun Sekar;
Azees, M.;
Dash, Chandra Sekhar;
Nayyar, Anand

Publication type:

Article

An Adaptive Digital Neural Network-Like-PID Control Law Design for Fuel Cell System Based on FPGA Technique.

Published in:

Journal of Engineering (17264073), 2020, v. 26, n. 9, p. 24, doi. 10.31026/j.eng.2020.09.03

By:

Al-Rubaye, Wajdi T. Joudah;
Al-Araji, Ahmed S.;
Dhahad, Hayder A.

Publication type:

Article

An Improved Throughput for Non-Binary Low-Density-Parity-Check Decoder.

Published in:

Computer Engineering & Applications Journal, 2020, v. 9, n. 3, p. 165, doi. 10.18495/comengapp.v9i3.345

By:

Olajide, Omowuyi;
Abdulrazaq, Bashir;
Adedokun, Adewale;
Umoh, Ime;
Bello, Akan

Publication type:

Article

Implementation of VIP for bus interface logic of 32-bit processor using System Verilog.

Published in:

Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials, 2018, v. 48, n. 4, p. 205, doi. 10.33180/InfMIDEM2018.402

By:

Ponkumar, D. David Neels;
Jagatheeswari, P.;
Samuel, T. S. Arun

Publication type:

Article

LOW POWER AND AREA EFFICIENT FFT PROCESSOR USING RADIX-2<sup>4</sup> FEED FORWARD MULTIPATH DELAY COMMUTATOR FOR WIRELESS COMMUNICATION.

Published in:

i-Manager's Journal on Wireless Communication Networks, 2019, v. 8, n. 3, p. 10, doi. 10.26634/jwcn.8.3.17115

By:

PADMA, C.;
JAGADAMBA, P.;
REDDY, P. RAMANA

Publication type:

Article

On regular temporal logics with past.

Published in:

Acta Informatica, 2010, v. 47, n. 4, p. 251, doi. 10.1007/s00236-010-0118-3

By:

Dax, Christian;
Klaedtke, Felix;
Lange, Martin

Publication type:

Article

A REVIEW OF IMAGE PROCESSING SYSTEMS: RECENT TRENDS AND FUTURE RESEARCH DIRECTIONS.

Published in:

Annals of the University Dunarea de Jos of Galati: Fascicle II, Mathematics, Physics, Theoretical Mechanics, 2015, v. 38, n. 1, p. 60

By:

Chiuchisan, Iuliana;
Popa, Valentin

Publication type:

Article

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer.

Published in:

Computers, Materials & Continua, 2022, v. 72, n. 3, p. 6079, doi. 10.32604/cmc.2022.027404

By:

Sha Li;
Qiao Meng;
Tariq, Irfan;
Xi Chen

Publication type:

Article

An improved Line-Drawing Algorithm for Arbitrary Fractional Frequency Divider/Multiplier Based on FPGA.

Published in:

Journal of Engineering Science & Technology Review, 2013, v. 6, n. 5, p. 90

By:

Jian-guang SHEN;
Tao TAO;
Xue-song MEI;
Mu-xun XU;
Shan-hui LIU

Publication type:

Article

Design, Implementation and Optimization of Highly Efficient UART.

Published in:

IUP Journal of Science & Technology, 2009, v. 5, n. 4, p. 21

By:

Sharma, Parul;
Gupta, Ashutosh

Publication type:

Article

INSTANCE-SPECIFIC SOLUTIONS FOR ACCELERATING THE CKY PARSING OF LARGE CONTEXT-FREE GRAMMARS.

Published in:

International Journal of Foundations of Computer Science, 2004, v. 15, n. 2, p. 403, doi. 10.1142/S0129054104002492

By:

Bordim, Jacir L.;
Barra, Oscar H.;
Ito, Yasuaki;
Nakano, Koji

Publication type:

Article

A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment.

Published in:

Radioengineering, 2016, v. 25, n. 1, p. 89, doi. 10.13164/re.2016.0089

By:

GONZALEZ-DIAZ, Victor R.;
MUNOZ-PACHECO, Jesus M.;
ESPINOSA-FLORES-VERDAD, Guillermo;
SANCHEZ-GASPARIANO, Luis A.

Publication type:

Article

Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design.

Published in:

Pertanika Journal of Science & Technology, 2024, v. 32, n. 1, p. 31, doi. 10.47836/pjst.32.1.02

By:

Suhaili, Shamsiah;
Julai, Norhuzaimin;
Sapawi, Rohana;
Rajaee, Nordiana

Publication type:

Article

ROM and recursion free high accuracy approximation of base-2 logarithm using MacLaurin series.

Published in:

Electronics Letters (Wiley-Blackwell), 2018, v. 54, n. 10, p. 622, doi. 10.1049/el.2018.0052

By:

Khan, A.;
Kareem, P.;
Kyung, C. M.

Publication type:

Article

Self-adjusting sensing circuit without speed penalty for reliable STT-MRAM.

Published in:

Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 4, p. 224, doi. 10.1049/el.2016.3877

By:

Ryu, J.-W.;
Kwon, K.-W.

Publication type:

Article

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing.

Published in:

Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 19, p. 1618, doi. 10.1049/el.2016.2294

By:

Labrado, C.;
Thapliyal, H.

Publication type:

Article

Comparison of Verilog-A compact modelling strategies for spintronic devices.

Published in:

Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 19, p. 1353, doi. 10.1049/el.2014.1083

By:

Jabeur, K.;
Bernard-Granger, F.;
Di Pendina, G.;
Prenat, G.;
Dieny, B.

Publication type:

Article

Real-time FPGA-based implementation of color image edge detection algorithm.

Published in:

Chinese Journal of Liquid Crystal & Displays, 2015, v. 30, n. 1, p. 143, doi. 10.3788/YJYXS20153001.0143

By:

CHEN Hu;
LING Chao-dong;
ZHANG Hao;
YANG Xiao;
TANG Wei

Publication type:

Article

Design and implementation of LCD controller with special requirement.

Published in:

Chinese Journal of Liquid Crystal & Displays, 2015, v. 30, n. 1, p. 109, doi. 10.3788/YJYXS20153001.0109

By:

LIU Liang

Publication type:

Article

FPGA Implementation of Mutual Authentication Protocol for Medication Security System.

Published in:

Journal of Low Power Electronics & Applications, 2021, v. 11, n. 4, p. 48, doi. 10.3390/jlpea11040048

By:

Lin, Wei-Chen;
Huang, Po-Kai;
Pan, Chung-Long;
Huang, Yu-Jung

Publication type:

Article

Circuit Architecture Test Verification Based on Hardware Software Co-design with ModelSim.

Published in:

IETE Journal of Research, 2013, v. 59, n. 2, p. 132, doi. 10.4103/0377-2063.113032

By:

Das, Sunil R.;
Jun-Feng Li;
Nayak, Amiya R.;
Assaf, Mansour H.;
Petriu, Emil M.;
Biswas, Satyendra N.

Publication type:

Article

A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation.

Published in:

IETE Journal of Research, 2012, v. 58, n. 3, p. 181, doi. 10.4103/0377-2063.97323

By:

Brinson, Mike E.;
Jahn, Stefan;
Nabijou, H.

Publication type:

Article

Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits.

Published in:

IETE Journal of Research, 2012, v. 58, n. 3, p. 179, doi. 10.4103/0377-2063.97322

By:

Bhattacharyya, A. B.;
Grabinski, Wladek

Publication type:

Article

System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL.

Published in:

IETE Journal of Research, 2012, v. 58, n. 2, p. 107, doi. 10.4103/0377-2063.96177

By:

Das, Sunil R.;
Biswas, Satyendra N.;
Biswas, Dhruv;
Petriu, Emil M.;
Assaf, Mansour H.

Publication type:

Article

FPGA-based Low Power Audio Subword Sorter Unit.

Published in:

IETE Journal of Research, 2009, v. 55, n. 6, p. 260, doi. 10.4103/0377-2063.58978

By:

Karthigaikumar, P.;
Baskaran, K.

Publication type:

Article

An Efficient FPGA-Based Welch Power Spectral Density for Real-Time Applications.

Published in:

Journal of Circuits, Systems & Computers, 2025, v. 34, n. 5, p. 1, doi. 10.1142/S0218126625501270

By:

Nair, Suma;
James, Britto Pari

Publication type:

Article

Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method.

Published in:

Journal of Circuits, Systems & Computers, 2025, v. 34, n. 5, p. 1, doi. 10.1142/S0218126625501233

By:

Behera, Niharika;
Pradhan, Manoranjan;
Kumar Bhoi, Bandan

Publication type:

Article