Works matching DE "VERILOG (Computer hardware description language)"

Results: 135

Design and Implementation of a Secure and Accurate Electronic Voting Machine Using Verilog on Zynq FPGA.

Published in:

Journal of Mobile Multimedia, 2025, v. 21, n. 3/4, p. 505, doi. 10.13052/jmm1550-4646.213410

By:

Harsha, Lekkala Chetan;
Bharatula, Sita Devi;
Reddy, B. Naresh Kumar;
Sarangam, K.

Publication type:

Article

Hardware Implementation of Local Mean Decomposition.

Published in:

Journal of Information Science & Engineering, 2017, v. 33, n. 1, p. 51

By:

PEI-YIN CHEN;
YEN-CHEN LAI;
PING-HSUAN LAI

Publication type:

Article

A Quasi-Delay-Insensitive Microprocessor Core Implementation for Microcontrollers.

Published in:

Journal of Information Science & Engineering, 2009, v. 25, n. 2, p. 543

By:

CHANG-JIU CHEN;
WEI-MIN CHENG;
HUNG-YUE TSAI;
JEN-CHIEH WU

Publication type:

Article

基于FPGA的双三相永磁同步电机伺服控制系统.

Published in:

Electronic Science & Technology, 2022, v. 35, n. 12, p. 49, doi. 10.16180/j.cnki.issn1007-7820.2022.12.007

By:

袁庆庆;
胡旭;
刘志勇;
马婷;
蒋全

Publication type:

Article

基于 Qt 的 Veribg 故障注入工具设计与实现.

Published in:

Experimental Technology & Management, 2019, v. 36, n. 1, p. 153, doi. 10.16791/j.cnki.sjg.2019.01.036

By:

王洁;
康俊杰;
HOU Gang;
于健海

Publication type:

Article

FPGA based Hardware Implementation of k-Nearest Neighbors(k-NN) Algorithm using the Manhattan Distance Metric for Binary Classification Tasks.

Published in:

Grenze International Journal of Engineering & Technology (GIJET), 2025, v. 11, n. Part1, p. 819

By:

Arumilli, Vamsi SriKrishna;
Ghatta, Asish Krishna;
Sabari, Gowshith;
A. S., Remya Ajai

Publication type:

Article

ineuralFPGA: Implementation of an Optimized DNN Model for Real-Time Applications.

Published in:

Ingénierie des Systèmes d'Information, 2025, v. 30, n. 4, p. 1101, doi. 10.18280/isi.300425

By:

Jain, Vineet;
Sharma, Abhishek;
Jain, Prateek;
Bezerra, Augusto;
Sharma, Sunil;
Alasmari, Sultan

Publication type:

Article

An efficient ultra-wideband digital transceiver for wireless applications on the field-programmable gate array platform.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2023, v. 13, n. 4, p. 4432, doi. 10.11591/ijece.v13i4.pp4432-4440

By:

Ramachandragowda, Santhosh Kumar;
Ramakrishna, Devaraju;
Narendra, Rajashree

Publication type:

Article

Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2023, v. 13, n. 2, p. 1346, doi. 10.11591/ijece.v13i2.pp1346-1357

By:

Azhari, Zul Imran;
Setumin, Samsul;
Noorsal, Emilia;
Abdullah, Mohd Hanapiah

Publication type:

Article

Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2018, v. 8, n. 5, p. 3544, doi. 10.11591/ijece.v8i5.pp3544-3549

By:

Renuka, G.;
Shree, V. Usha;
Reddy, P. Chandra Sekhar

Publication type:

Article

Study of Data Security Algorithms using Verilog HDL.

Published in:

International Journal of Electrical & Computer Engineering (2088-8708), 2015, v. 5, n. 5, p. 1092

By:

Sumathi, M.;
Nirmala, D.;
Rajkumar, R. Immanuel

Publication type:

Article

An improved Line-Drawing Algorithm for Arbitrary Fractional Frequency Divider/Multiplier Based on FPGA.

Published in:

Journal of Engineering Science & Technology Review, 2013, v. 6, n. 5, p. 90

By:

Jian-guang SHEN;
Tao TAO;
Xue-song MEI;
Mu-xun XU;
Shan-hui LIU

Publication type:

Article

Massively Parallel Combinational Binary Neural Networks for Edge Processing.

Published in:

Electrotechnical Review / Elektrotehniski Vestnik, 2019, v. 86, n. 1/2, p. 47

By:

Murovič, Tadej;
Trost, Andrej

Publication type:

Article

Synthesizable High Level Hardware Descriptions.

Published in:

New Generation Computing, 2010, v. 28, n. 4, p. 339, doi. 10.1007/s00354-008-0093-1

By:

Gillenwater, Jennifer;
Malecha, Gregory;
Salama, Cherif;
Zhu, Angela;
Taha, Walid;
Grundy, Jim;
O'leary, John

Publication type:

Article

Circuit realization and FPGA-based implementation of a fractional-order chaotic system for cancellable face recognition.

Published in:

Multimedia Tools & Applications, 2024, v. 83, n. 34, p. 81565, doi. 10.1007/s11042-023-15867-z

By:

Badr, Iman S.;
Radwan, Ahmed G.;
EL-Rabaie, El-Sayed M.;
Said, Lobna A.;
El-Shafai, Walid;
El-Banby, Ghada M.;
Abd El-Samie, Fathi E.

Publication type:

Article

Content addressable memory (CAM) based robust anonymous authentication and integrity preservation scheme for wireless body area networks (WBAN).

Published in:

Multimedia Tools & Applications, 2024, v. 83, n. 7, p. 20429, doi. 10.1007/s11042-023-16257-1

By:

Rajasekaran, Arun Sekar;
Azees, M.;
Dash, Chandra Sekhar;
Nayyar, Anand

Publication type:

Article

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system.

Published in:

Multimedia Tools & Applications, 2017, v. 76, n. 11, p. 13197, doi. 10.1007/s11042-016-3736-0

By:

Sathish Shet, K.;
Aswath, A.;
Hanumantharaju, M.;
Gao, Xiao-Zhi

Publication type:

Article

SV DPI技术在FPGA仿真验证的应用探讨.

Published in:

Computer Measurement & Control, 2018, v. 26, n. 6, p. 264, doi. 10.16526/j.cnki.11-4762/tp.2018.06.067

By:

祝周荣;
关俊强;
李前进;
赵超;
刘芳汝

Publication type:

Article

基于FPGA 的 RC4 加密算法设计及实现.

Published in:

Computer Measurement & Control, 2018, v. 26, n. 2, p. 252, doi. 10.16526/j.cnki.11-4762/tp.2018.02.062

By:

苗三立;
左金印;
宋宇飞

Publication type:

Article

Implementation of VIP for bus interface logic of 32-bit processor using System Verilog.

Published in:

Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials, 2018, v. 48, n. 4, p. 205, doi. 10.33180/InfMIDEM2018.402

By:

Ponkumar, D. David Neels;
Jagatheeswari, P.;
Samuel, T. S. Arun

Publication type:

Article

LOW POWER AND AREA EFFICIENT FFT PROCESSOR USING RADIX-2<sup>4</sup> FEED FORWARD MULTIPATH DELAY COMMUTATOR FOR WIRELESS COMMUNICATION.

Published in:

i-Manager's Journal on Wireless Communication Networks, 2019, v. 8, n. 3, p. 10, doi. 10.26634/jwcn.8.3.17115

By:

PADMA, C.;
JAGADAMBA, P.;
REDDY, P. RAMANA

Publication type:

Article

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm.

Published in:

Energies (19961073), 2024, v. 17, n. 8, p. 1870, doi. 10.3390/en17081870

By:

Wu, Caiyun;
Zhang, Kai;
Zhang, Xin

Publication type:

Article

Large-Signal DG-MOSFET Modelling for RFID Rectification.

Published in:

Advances in Condensed Matter Physics, 2016, p. 1, doi. 10.1155/2016/8017139

By:

Rodríguez, R.;
González, B.;
García, J.;
Lázaro, A.;
Iñiguez, B.;
Hernández, A.

Publication type:

Article

The Study of PID AQM Algorithm for FPGA Implementation.

Published in:

Journal of Multimedia, 2015, v. 10, n. 1, p. 22, doi. 10.4304/jmm.10.01.22-27

By:

Xiaoping Yang;
Xiaojing Wang;
Te Di;
Chao Niu

Publication type:

Article

Desing of VLSI Architecture for a flexible testbed of Artificial Neural Network for training and testing on FPGA.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2024, v. 6, n. 1, p. 30, doi. 10.31838/jvcs/06.01.06

By:

Arora, Gurmeet Kaur

Publication type:

Article

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation.

Published in:

International Journal of Information Security, 2024, v. 23, n. 1, p. 1, doi. 10.1007/s10207-023-00717-8

By:

Rajasekaran, Arun Sekar;
Azees, M.

Publication type:

Article

Design and Implementation of Field-Programmable Gate Array Based Fast Fourier Transform Co-Processor Using Verilog Hardware Description Language.

Published in:

Progress in Electromagnetics Research B, 2021, v. 92, p. 47, doi. 10.2528/pierb20122806

By:

Yung-Chong Lee;
Yee-Kit Chan;
Voon-Chet Koo

Publication type:

Article

FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier.

Published in:

International Review on Modelling & Simulations, 2019, v. 12, n. 2, p. 66, doi. 10.15866/iremos.v12i2.16322

By:

Alkurwy, Salah;
Al-Azawi, Saad;
Al Darraji, Noor

Publication type:

Article

Design Of Cricket Game and Display System Using Verilog HDL.

Published in:

e-Journal of Science & Technology, 2017, v. 12, n. 1, p. 91

By:

Sreehari, Mogulluri;
Sarath, P. Sreeram;
Kumar, P. Vinod;
Noorbasha, Fazal

Publication type:

Article

Implementation of 90 nm CMOS LFSR Test Vector Generator of FPGA Floating Point Arithmetic Unit.

Published in:

e-Journal of Science & Technology, 2013, v. 8, n. 3, p. 85

By:

Noorbasha, Fazal;
Madhav, Ch.S.Venu;
Hu, Jacqueline;
Vardhan Reddy, GSRK Harsha;
Sireesha, Rolla;
Charan Tej, P.Joshi Ram

Publication type:

Article

A Multiplier-Less Lifting Scheme Based DWT Structure.

Published in:

International Review on Computers & Software, 2014, v. 9, n. 1, p. 203

By:

Akilandeswari, A.

Publication type:

Article

An FPGA Resource Adaptable General Neural Network Accelerator.

Published in:

International Journal of Simulation: Systems, Science & Technology, 2022, v. 23, n. 2, p. 1, doi. 10.5013/IJSSST.a.23.02.05

By:

Chengsen Dong;
Zheng Xie

Publication type:

Article

Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL.

Published in:

Journal of Supercomputing, 2023, v. 79, n. 9, p. 9866, doi. 10.1007/s11227-023-05051-3

By:

de Castro, Manuel;
Osorio, Roberto R.;
Vilariño, David L.;
Gonzalez-Escribano, Arturo;
Llanos, Diego R.

Publication type:

Article

FPGA acceleration on a multi-layer perceptron neural network for digit recognition.

Published in:

Journal of Supercomputing, 2021, v. 77, n. 12, p. 14356, doi. 10.1007/s11227-021-03849-7

By:

Westby, Isaac;
Yang, Xiaokun;
Liu, Tao;
Xu, Hailu

Publication type:

Article

General SPICE Modeling Procedure for Double-Gate Tunnel Field-Effect Transistors.

Published in:

Journal of Information & Communication Convergence Engineering, 2016, v. 14, n. 2, p. 115, doi. 10.6109/jicce.2016.14.2.115

By:

Najam, Syed Faraz;
Michael Loong Peng Tan;
Yun Seop Yu

Publication type:

Article

Oversampling advances in millimeter-wave scan imaging using inexpensive neon indicator lamp detectors.

Published in:

Optical Engineering, 2013, v. 52, n. 6, p. 1, doi. 10.1117/1.OE.52.6.063202

By:

Levanon, Assaf;
Kopeika, Natan S.;
Yitzhaky, Yitzhak;
Abramovich, Amir;
Rozban, Daniel;
Joseph, Hezi;
Aharon, Avihai;
Belenky, Alex;
Gefen, Michael;
Yadid-Pecht, Orly

Publication type:

Article

A NOVEL BASED APPROACH FOR A HIGH SPEED 24 BIT MULTIPLIER.

Published in:

i-Manager's Journal on Electronics Engineering, 2014, v. 4, n. 4, p. 21, doi. 10.26634/jele.4.4.3198

By:

KUMAR, DUVVURU PRAVEEN;
BHARATHI, M.;
TUNGA, MOUNIKA

Publication type:

Article

TIMING COMPUTING IN ASYNCHRONOUS DIGITAL AUTOMATA.

Published in:

Scientific Research & Education in the Air Force - AFASES, 2012, v. 1, p. 623

By:

Timis, Mihai;
Valachi, Alexandru

Publication type:

Article

A High-Performance and Cost-Effective Field Programmable Gate Array-Based Motor Drive Emulator.

Published in:

Micromachines, 2023, v. 14, n. 10, p. 1864, doi. 10.3390/mi14101864

By:

Hernandez, Julio;
Rangel-Magdaleno, Jose de Jesus;
Morales-Caporal, Roberto

Publication type:

Article

ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator.

Published in:

Micromachines, 2021, v. 12, n. 7, p. 838, doi. 10.3390/mi12070838

By:

Hwang, Dong Hyun;
Han, Chang Yeop;
Oh, Hyun Woo;
Lee, Seung Eun

Publication type:

Article

Circuit Architecture Test Verification Based on Hardware Software Co-design with ModelSim.

Published in:

IETE Journal of Research, 2013, v. 59, n. 2, p. 132, doi. 10.4103/0377-2063.113032

By:

Das, Sunil R.;
Jun-Feng Li;
Nayak, Amiya R.;
Assaf, Mansour H.;
Petriu, Emil M.;
Biswas, Satyendra N.

Publication type:

Article

A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation.

Published in:

IETE Journal of Research, 2012, v. 58, n. 3, p. 181, doi. 10.4103/0377-2063.97323

By:

Brinson, Mike E.;
Jahn, Stefan;
Nabijou, H.

Publication type:

Article

Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits.

Published in:

IETE Journal of Research, 2012, v. 58, n. 3, p. 179, doi. 10.4103/0377-2063.97322

By:

Bhattacharyya, A. B.;
Grabinski, Wladek

Publication type:

Article

System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL.

Published in:

IETE Journal of Research, 2012, v. 58, n. 2, p. 107, doi. 10.4103/0377-2063.96177

By:

Das, Sunil R.;
Biswas, Satyendra N.;
Biswas, Dhruv;
Petriu, Emil M.;
Assaf, Mansour H.

Publication type:

Article

FPGA-based Low Power Audio Subword Sorter Unit.

Published in:

IETE Journal of Research, 2009, v. 55, n. 6, p. 260, doi. 10.4103/0377-2063.58978

By:

Karthigaikumar, P.;
Baskaran, K.

Publication type:

Article

Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions.

Published in:

Journal of Applied Mathematics, 2014, p. 1, doi. 10.1155/2014/194574

By:

Ning Zhou;
Xinyan Gao;
Jinzhao Wu;
Jianchao Wei;
Dakui Li

Publication type:

Article

Wu's Characteristic Set Method for System Verilog Assertions Verification.

Published in:

Journal of Applied Mathematics, 2013, p. 1, doi. 10.1155/2013/740194

By:

Xinyan Gao;
Ning Zhou;
Jinzhao Wu;
Dakui Li

Publication type:

Article

FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder.

Published in:

Bulletin of the National Research Centre, 2024, v. 48, n. 1, p. 1, doi. 10.1186/s42269-024-01285-0

By:

Elsayed, Ghada;
Abass, Eman S.

Publication type:

Article

DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG.

Published in:

i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 4, p. 38, doi. 10.26634/jcir.6.4.14864

By:

BHAGAT, S. M.;
BHANDARI, S. U.

Publication type:

Article

IMPLEMENTATION OF REVERSIBLE LOGIC GATE (PERES GATE) TO DESIGN A HALF ADDER FOR LOW POWER WITH REDUCED AREA AND IMPROVED EFFICIENCY.

Published in:

i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 3, p. 36, doi. 10.26634/jcir.6.3.14877

By:

NIRMALKAR, TRIPTI;
KANOUJIA, DEEPTI;
VARMA, KSHITIZ

Publication type:

Article