Works matching DE "TIMING circuits"


Results: 75
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    DESIGN TIMED FSM WITH VHDL MOORE PATTERN.

    Published in:
    Radio Electronics, Computer Science, Control, 2020, n. 2, p. 137, doi. 10.15588/1607-3274-2020-2-14
    By:
    • Mіroshnyk, M. A.;
    • Shkil, A. S.;
    • Kulak, E. N.;
    • Rakhlis, D. Y.;
    • Mіroshnyk, A. M.;
    • Malahov, N. V.
    Publication type:
    Article
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