A 3.1 GB/s, 8 Kb, ZERO PRECHARGE, PIPELINED, HIGHLY STABLE 2-PORT 8T SRAM DESIGN IN 65 nm.
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- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 8, p. -1, doi. 10.1142/S0218126613500692
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Works matching DE "STATIC random access memory design %26 construction"
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A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability.
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- Wireless Personal Communications, 2017, v. 94, n. 4, p. 3513, doi. 10.1007/s11277-016-3788-5
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