Works matching DE "STATIC random access memory chips"

Results: 63

Different Casues For Reduction Of Lekage Current In Sram: A State Of The Art.

Published in:

Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 18, doi. 10.31838/jvcs/02.01.05

By:

KAVITHA, M.

Publication type:

Article

Super-Threshold Adiabatic FinFET SRAM with PAL-2N Logic.

Published in:

Metallurgical & Mining Industry, 2015, n. 9, p. 1134

By:

Yuejie Zhang;
Jianping Hu;
Tianfang Ma;
Beibei Qi

Publication type:

Article

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission.

Published in:

Advances in Mechanical Engineering (Sage Publications Inc.), 2013, v. 5, p. 1, doi. 10.1155/2013/783673

By:

Jie Zhang;
Yong Guan;
Chunjing Mao

Publication type:

Article

Circuits and Simulation of Quaternary SRAM Using Quantum Dot Channel Field Effect Transistors (QDC-FETs).

Published in:

International Journal of High Speed Electronics & Systems, 2018, v. 27, n. 1/2, p. N.PAG, doi. 10.1142/S0129156418400049

By:

Saman, Bander;
Kondo, Jun;
Chandy, J.;
Jain, F. C.

Publication type:

Article

Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power.

Published in:

Circuits, Systems & Signal Processing, 2017, v. 36, n. 8, p. 3047, doi. 10.1007/s00034-016-0466-5

By:

Nayak, Debasish;
Acharya, Debiprasad;
Mahapatra, Kamalakanta

Publication type:

Article

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance.

Published in:

Circuits, Systems & Signal Processing, 2016, v. 35, n. 9, p. 3066, doi. 10.1007/s00034-015-0199-x

By:

Reniwal, Bhupendra;
Vijayvargiya, Vikas;
Vishvakarma, Santosh;
Dwivedi, Devesh

Publication type:

Article

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.

Published in:

Circuits, Systems & Signal Processing, 2016, v. 35, n. 2, p. 385, doi. 10.1007/s00034-015-0086-5

By:

Kushwah, C.;
Vishvakarma, S.;
Dwivedi, D.

Publication type:

Article

In‐memory multibit multiplication and accumulation based on an automatic pulse generation circuit.

Published in:

Electronics Letters (Wiley-Blackwell), 2023, v. 59, n. 22, p. 1, doi. 10.1049/ell2.13036

By:

Bai, Su;
Guo, Jiaqi;
Liu, Yunlong;
Xu, Yaohua;
Peng, Chunyu;
Wu, Xiulong

Publication type:

Article

An energy‐efficient floating‐point compute SRAM with pipelined in‐memory bit‐parallel exponent and bitwise mantissa processing.

Published in:

Electronics Letters (Wiley-Blackwell), 2023, v. 59, n. 14, p. 1, doi. 10.1049/ell2.12885

By:

Mai, Yangzhan;
Wang, Mingyu;
Zhong, Baiqing;
Zhang, Chuanghao;
Zhang, Yicong;
Yu, Zhiyi

Publication type:

Article

Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture.

Published in:

Computer Journal, 2016, v. 59, n. 5, p. 685, doi. 10.1093/comjnl/bxv103

By:

JU-HEE CHOI;
GI-HO PARK

Publication type:

Article

A Soft Error Study on Tri-gate Based FinFET and Junctionless-FinFET 6T SRAM Cell - A Comparison.

Published in:

Telkomnika, 2016, v. 14, n. 4, p. 1299, doi. 10.12928/TELKOMNIKA.v14i4.3458

By:

Chitra, P.;
Ravi, S.;
Ramakrishnan, V. N.

Publication type:

Article

Reliable Implementation on SRAM-based FPGA using Evolutionary Methods.

Published in:

IETE Journal of Research, 2013, v. 59, n. 5, p. 597, doi. 10.4103/0377-2063.123766

By:

Jahanirad, Hadi;
Mohammadi, Karim

Publication type:

Article

A 28-nm 32 Kb SRAM For Low-V<sub>MIN</sub> Applications Using Write and Read Assist Techniques.

Published in:

Radioengineering, 2017, v. 26, n. 3, p. 772, doi. 10.13164/re.2017.0772

By:

KUMAR, Satyendra;
SAHA, Kaushik;
GUPTA, Hariom

Publication type:

Article

Performance analysis of junctionless DG-MOSFET-based 6T-SRAM with gate-stack configuration.

Published in:

Micro & Nano Letters (Wiley-Blackwell), 2018, v. 13, n. 6, p. 838, doi. 10.1049/mnl.2017.0702

By:

Tayal, Shubham;
Nandi, Ashutosh

Publication type:

Article

Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications.

Published in:

Micro & Nano Letters (Wiley-Blackwell), 2016, v. 11, n. 12, p. 828, doi. 10.1049/mnl.2016.0442

By:

Makosiej, Adam;
Gupta, Navneet;
Vakul, Naga;
Vladimirescu, Andrei;
Cotofana, Sorin;
Mahapatra, Santanu;
Amara, Amara;
Anghel, Costin

Publication type:

Article

Mehr Bedienkomfort und erweiterte Trace-Unterstützung.

Published in:: Elektronik Industrie, 2024, p. 45
Publication type:: Article

Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits.

Published in:

VLSI Design, 2013, p. 1, doi. 10.1155/2013/984376

By:

Zheng Xie;
Edwards, Doug

Publication type:

Article

Design and Analysis of Three New SRAM Cells.

Published in:

Majlesi Journal of Electrical Engineering, 2012, v. 6, n. 4, p. 30

By:

Ebrahimi, Amir;
Kargaran, Ehsan;
Golmakani, Abbas

Publication type:

Article

LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER.

Published in:

Journal of Circuits, Systems & Computers, 2013, v. 22, n. 7, p. -1, doi. 10.1142/S021812661350062X

By:

SINGH, AJAY KUMAR;
SEONG, MAH MENG;
PRABHU, C. M. R.

Publication type:

Article

Design and Analysis of Low Power Memristor Based Non-volatile 4T SRAM Cell with Power Reduction Techniques.

Published in:

Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 1/2, p. 23

By:

BORKAR, NEHA;
AKASHE, SHYAM

Publication type:

Article

Optimization of Leakage Current and Leakage Power on 4x4 Array with SVL Technique Employed 7T SRAM Cell in Nanometer Regime.

Published in:

Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 4, p. 291

By:

SINGH, SHALINI;
AKASHE, SHYAM

Publication type:

Article

Analysis of FinFET Based 8T SRAM Cell Using Adaptive Voltage Level Techniques.

Published in:

Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 4, p. 283

By:

SHARMA, JOSHIKA;
KHANDELWAL, SAURABH;
AKASHE, SHYAM

Publication type:

Article

Impact of Design Parameters on 6T and 8T SRAM cells at 45nm technology.

Published in:

Journal of Active & Passive Electronic Devices, 2015, v. 10, n. 1, p. 41

By:

SHARMA, JOSHIKA;
AKASHE, SHYAM

Publication type:

Article

Low Power SRAM cell Design Using Independent Gate FinFET.

Published in:

Journal of Active & Passive Electronic Devices, 2014, v. 9, n. 2/3, p. 101

By:

SIKARWAR, VANDNA;
KHANDELWAL, SAURABH;
AKASHE, SHYAM

Publication type:

Article

Radiation Tolerant SRAM Cell Design in 65nm Technology.

Published in:

Journal of Electronic Testing, 2021, v. 37, n. 2, p. 255, doi. 10.1007/s10836-021-05941-5

By:

Wang, JianAn;
Wu, Xue;
Tian, Haonan;
Li, Lixiang;
Shi, Shuting;
Chen, Li

Publication type:

Article

Analysing NBTI Impact on SRAMs with Resistive Defects.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 5, p. 637, doi. 10.1007/s10836-017-5685-6

By:

Martins, M.;
Medeiros, G.;
Copetti, T.;
Vargas, F.;
Bolzani Poehls, L.

Publication type:

Article

A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 4, p. 449, doi. 10.1007/s10836-017-5659-8

By:

Niaraki Asli, Rahebeh;
Taghipour, Shiva

Publication type:

Article

Reliability Model for Multiple-Error Protected Static Memories.

Published in:

Journal of Electronic Testing, 2017, v. 33, n. 2, p. 189, doi. 10.1007/s10836-017-5649-x

By:

Jahanirad, Hadi

Publication type:

Article

A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs.

Published in:

Journal of Electronic Testing, 2016, v. 32, n. 6, p. 749, doi. 10.1007/s10836-016-5622-0

By:

Ruan, Aiwu;
Huang, Haiyang;
Wang, Jingwu;
Zhao, Yifan

Publication type:

Article

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets.

Published in:

Journal of Electronic Testing, 2016, v. 32, n. 2, p. 137, doi. 10.1007/s10836-016-5573-5

By:

Li, Yuanqing;
Li, Lixiang;
Ma, Yuan;
Chen, Li;
Liu, Rui;
Wang, Haibin;
Wu, Qiong;
Newton, Michael;
Chen, Mo

Publication type:

Article

Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.

Published in:

Journal of Electronic Testing, 2015, v. 31, n. 5/6, p. 561, doi. 10.1007/s10836-015-5549-x

By:

Li, Lixiang;
Li, Yuanqing;
Wang, Haibin;
Liu, Rui;
Wu, Qiong;
Newton, Michael;
Ma, Yuan;
Chen, Li

Publication type:

Article

Editorial.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 741, doi. 10.1007/s10836-013-5424-6

By:

Agrawal, Vishwani D.

Publication type:

Article

Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 6, p. 779, doi. 10.1007/s10836-013-5418-4

By:

Bolchini, Cristiana;
Miele, Antonio;
Sandionigi, Chiara

Publication type:

Article

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 4, p. 457, doi. 10.1007/s10836-013-5393-9

By:

Thibeault, C.;
Hariri, Y.;
Hasan, S. R.;
Hobeika, C.;
Savaria, Y.;
Audet, Y.;
Tazi, F. Z.

Publication type:

Article

A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.

Published in:

Journal of Electronic Testing, 2013, v. 29, n. 3, p. 341, doi. 10.1007/s10836-013-5387-7

By:

Alderighi, M.;
Casini, F.;
D'Angelo, S.;
Gravina, A.;
Liberali, V.;
Mancini, M.;
Musazzi, P.;
Pastore, S.;
Sassi, M.;
Sorrenti, G.

Publication type:

Article

A Novel SRAM PUF Stability Improvement Method Using Ionization Irradiation.

Published in:

Electronics (2079-9292), 2020, v. 9, n. 9, p. 1498, doi. 10.3390/electronics9091498

By:

Zhang, Xu;
Jiang, Chunsheng;
Gu, Ke;
Zhong, Le;
Fang, Wen;
Dai, Gang

Publication type:

Article

A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability.

Published in:

Journal of Low Power Electronics & Applications, 2018, v. 8, n. 4, p. 41, doi. 10.3390/jlpea8040041

By:

Tripathi, Tripti;
Chauhan, Durg Singh;
Singh, Sanjay Kumar

Publication type:

Article

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors.

Published in:

Journal of Low Power Electronics & Applications, 2018, v. 8, n. 3, p. 28, doi. 10.3390/jlpea8030028

By:

Gu, Yunfei;
Yan, Dengxue;
Verma, Vaibhav;
Wang, Pai;
Stan, Mircea R.;
Zhang, Xuan

Publication type:

Article

Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications.

Published in:

Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 24, doi. 10.3390/jlpea7030024

By:

Singh, Pooran;
Vishvakarma, Santosh Kumar

Publication type:

Article

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability.

Published in:

Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 23, doi. 10.3390/jlpea7030023

By:

Mittal, Sparsh;
Rujia Wang;
Vetter, Jeffrey

Publication type:

Article

Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology.

Published in:

Journal of Engineering Science & Technology Review, 2016, v. 9, n. 5, p. 145

By:

Apostolidis, G.;
Balobas, D.;
Konofaos, N.

Publication type:

Article

Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell.

Published in:

Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2016, v. 41, n. 8, p. 2945, doi. 10.1007/s13369-016-2047-0

By:

Kavitha, M.;
Govindaraj, T.

Publication type:

Article

SRAM cell with asymmetric pass-gate nMOSFETs for embedded memory applications.

Published in:

Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 13, p. 1172, doi. 10.1049/el.2016.0938

By:

Weiwei He;
Jing Chen;
Jiexin Luo;
Zhan Chai;
Xi Wang

Publication type:

Article

Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells.

Published in:

Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 24, p. 1823, doi. 10.1049/el.2014.2540

By:

Gherman, V.;
Cartron, M.

Publication type:

Article

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.

Published in:

Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 1035, doi. 10.3906/elk-1502-124

By:

RAJAEI, Ramin;
ASGARI, Bahar;
TABANDEH, Mahmoud;
FAZELI, Mahdi

Publication type:

Article

DESIGN OF DUAL-POWER-SUPPLY-SRAM AND MEASURE OF ACTIVE AND STANDBY MODE POWER BY USING BL CALCULATOR.

Published in:

i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 2, p. 19

By:

LOKESH, P.;
MUNIREDDY, T.;
PESHA, J. V.

Publication type:

Article

COMPARISON OF POWER AND LATENCY OPTIMIZED 7T SRAM BIT-CELL WITH 6T SRAM BIT-CELL.

Published in:

i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 2, p. 8, doi. 10.26634/jcir.6.2.14760

By:

SHIVAPRAKASH, G.;
SURESH, D. S.

Publication type:

Article

PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW.

Published in:

i-Manager's Journal on Circuits & Systems, 2017, v. 6, n. 1, p. 25

By:

TIWARI, NIDHI;
NEEMA, VAIBHAV;
RANGRA, KAMAL J.;
SHARMA, YOGESH CHANDRA

Publication type:

Article

SRAM WRITE OPERATION USING WRITE ASSIST CIRCUIT TECHNIQUE AT LOW SUPPLY VOLTAGES.

Published in:

i-Manager's Journal on Circuits & Systems, 2016, v. 4, n. 4, p. 1, doi. 10.26634/jcir.4.4.12392

By:

REDDY, A. PULLA;
SREENIVASULU, G.;
CHARY, R. VEERABADRA

Publication type:

Article

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing.

Published in:

International Journal of Reconfigurable Computing, 2017, p. 1, doi. 10.1155/2017/7021056

By:

Asghar, Ali;
Iqbal, Muhammad Mazher;
Ahmed, Waqar;
Ali, Mujahid;
Parvez, Husain;
Rashid, Muhammad

Publication type:

Article