Works matching DE "STATIC random access memory chips"
Results: 60
In‐memory multibit multiplication and accumulation based on an automatic pulse generation circuit.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2023, v. 59, n. 22, p. 1, doi. 10.1049/ell2.13036
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- Article
An energy‐efficient floating‐point compute SRAM with pipelined in‐memory bit‐parallel exponent and bitwise mantissa processing.
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- Electronics Letters (Wiley-Blackwell), 2023, v. 59, n. 14, p. 1, doi. 10.1049/ell2.12885
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- Article
Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture.
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- Computer Journal, 2016, v. 59, n. 5, p. 685, doi. 10.1093/comjnl/bxv103
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- Article
Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell.
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- Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2016, v. 41, n. 8, p. 2945, doi. 10.1007/s13369-016-2047-0
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- Article
Different Casues For Reduction Of Lekage Current In Sram: A State Of The Art.
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- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 18, doi. 10.31838/jvcs/02.01.05
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- Article
A Novel Approach to Design SRAM Cells for Low Leakage and Improved Stability.
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- Journal of Low Power Electronics & Applications, 2018, v. 8, n. 4, p. 41, doi. 10.3390/jlpea8040041
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- Article
Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors.
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- Journal of Low Power Electronics & Applications, 2018, v. 8, n. 3, p. 28, doi. 10.3390/jlpea8030028
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- Article
Ultra-Low Power, Process-Tolerant 10T (PT10T) SRAM with Improved Read/Write Ability for Internet of Things (IoT) Applications.
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- Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 24, doi. 10.3390/jlpea7030024
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- Article
DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability.
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- Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 23, doi. 10.3390/jlpea7030023
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- Article
Design and Simulation of 6T SRAM Cell Architectures in 32nm Technology.
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- Journal of Engineering Science & Technology Review, 2016, v. 9, n. 5, p. 145
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- Article
Design and Analysis of Three New SRAM Cells.
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- Majlesi Journal of Electrical Engineering, 2012, v. 6, n. 4, p. 30
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- Article
Reliable Implementation on SRAM-based FPGA using Evolutionary Methods.
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- IETE Journal of Research, 2013, v. 59, n. 5, p. 597, doi. 10.4103/0377-2063.123766
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- Article
Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM.
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- Journal of Nanotechnology, 2017, p. 1, doi. 10.1155/2017/4575013
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- Article
Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission.
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- Advances in Mechanical Engineering (Sage Publications Inc.), 2013, v. 5, p. 1, doi. 10.1155/2013/783673
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- Article
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures.
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- Journal of Supercomputing, 2018, v. 74, n. 7, p. 3388, doi. 10.1007/s11227-018-2389-3
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- Article
PS directory: a scalable multilevel directory cache for CMPs.
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- Journal of Supercomputing, 2015, v. 71, n. 8, p. 2847, doi. 10.1007/s11227-014-1332-5
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- Article
Editorial.
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- Journal of Electronic Testing, 2013, v. 29, n. 6, p. 741, doi. 10.1007/s10836-013-5424-6
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- Article
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms.
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- Journal of Electronic Testing, 2013, v. 29, n. 6, p. 779, doi. 10.1007/s10836-013-5418-4
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- Article
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.
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- Journal of Electronic Testing, 2013, v. 29, n. 4, p. 457, doi. 10.1007/s10836-013-5393-9
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- Article
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs.
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- Journal of Electronic Testing, 2013, v. 29, n. 3, p. 341, doi. 10.1007/s10836-013-5387-7
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- Article
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2017, v. 25, n. 2, p. 1035, doi. 10.3906/elk-1502-124
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- Article
Super-Threshold Adiabatic FinFET SRAM with PAL-2N Logic.
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- Metallurgical & Mining Industry, 2015, n. 9, p. 1134
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- Article
Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing.
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- International Journal of Reconfigurable Computing, 2017, p. 1, doi. 10.1155/2017/7021056
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- Article
AC_ICAP: A Flexible High Speed ICAP Controller.
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- International Journal of Reconfigurable Computing, 2015, p. 1, doi. 10.1155/2015/314358
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- Publication type:
- Article
Design and Analysis of Low Power Memristor Based Non-volatile 4T SRAM Cell with Power Reduction Techniques.
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- Journal of Active & Passive Electronic Devices, 2017, v. 12, n. 1/2, p. 23
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- Article
Optimization of Leakage Current and Leakage Power on 4x4 Array with SVL Technique Employed 7T SRAM Cell in Nanometer Regime.
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- Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 4, p. 291
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- Article
Analysis of FinFET Based 8T SRAM Cell Using Adaptive Voltage Level Techniques.
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- Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 4, p. 283
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- Article
Impact of Design Parameters on 6T and 8T SRAM cells at 45nm technology.
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- Journal of Active & Passive Electronic Devices, 2015, v. 10, n. 1, p. 41
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- Article
Low Power SRAM cell Design Using Independent Gate FinFET.
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- Journal of Active & Passive Electronic Devices, 2014, v. 9, n. 2/3, p. 101
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- Article
Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure.
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- Sensors (14248220), 2020, v. 20, n. 21, p. 6132, doi. 10.3390/s20216132
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- Article
DIAGNOSTIC TECHNIQUE SELECTION FOR SRAM LOGIC TYPE FAILURES.
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- Electronic Device Failure Analysis, 2018, v. 20, n. 2, p. 18, doi. 10.31399/asm.edfa.2018-2.p018
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- Article
SRAM cell with asymmetric pass-gate nMOSFETs for embedded memory applications.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 13, p. 1172, doi. 10.1049/el.2016.0938
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- Article
Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 24, p. 1823, doi. 10.1049/el.2014.2540
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- Article
COMPARISON OF POWER AND LATENCY OPTIMIZED 7T SRAM BIT-CELL WITH 6T SRAM BIT-CELL.
- Published in:
- i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 2, p. 8, doi. 10.26634/jcir.6.2.14760
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- Article
DESIGN OF DUAL-POWER-SUPPLY-SRAM AND MEASURE OF ACTIVE AND STANDBY MODE POWER BY USING BL CALCULATOR.
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- i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 2, p. 19
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- Article
PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW.
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- i-Manager's Journal on Circuits & Systems, 2017, v. 6, n. 1, p. 25
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- Publication type:
- Article
SRAM WRITE OPERATION USING WRITE ASSIST CIRCUIT TECHNIQUE AT LOW SUPPLY VOLTAGES.
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- i-Manager's Journal on Circuits & Systems, 2016, v. 4, n. 4, p. 1, doi. 10.26634/jcir.4.4.12392
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- Publication type:
- Article
LOW POWER AND HIGH PERFORMANCE SINGLE-ENDED SENSE AMPLIFIER.
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- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 7, p. -1, doi. 10.1142/S021812661350062X
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- Publication type:
- Article
Circuits and Simulation of Quaternary SRAM Using Quantum Dot Channel Field Effect Transistors (QDC-FETs).
- Published in:
- International Journal of High Speed Electronics & Systems, 2018, v. 27, n. 1/2, p. N.PAG, doi. 10.1142/S0129156418400049
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- Article
A 28-nm 32 Kb SRAM For Low-V<sub>MIN</sub> Applications Using Write and Read Assist Techniques.
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- Radioengineering, 2017, v. 26, n. 3, p. 772, doi. 10.13164/re.2017.0772
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- Publication type:
- Article
A Novel SRAM PUF Stability Improvement Method Using Ionization Irradiation.
- Published in:
- Electronics (2079-9292), 2020, v. 9, n. 9, p. 1498, doi. 10.3390/electronics9091498
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- Publication type:
- Article
Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power.
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- Circuits, Systems & Signal Processing, 2017, v. 36, n. 8, p. 3047, doi. 10.1007/s00034-016-0466-5
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- Publication type:
- Article
Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance.
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- Circuits, Systems & Signal Processing, 2016, v. 35, n. 9, p. 3066, doi. 10.1007/s00034-015-0199-x
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- Publication type:
- Article
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications.
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- Circuits, Systems & Signal Processing, 2016, v. 35, n. 2, p. 385, doi. 10.1007/s00034-015-0086-5
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- Article
Radiation Tolerant SRAM Cell Design in 65nm Technology.
- Published in:
- Journal of Electronic Testing, 2021, v. 37, n. 2, p. 255, doi. 10.1007/s10836-021-05941-5
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- Article
Analysing NBTI Impact on SRAMs with Resistive Defects.
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- Journal of Electronic Testing, 2017, v. 33, n. 5, p. 637, doi. 10.1007/s10836-017-5685-6
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- Article
Reliability Model for Multiple-Error Protected Static Memories.
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- Journal of Electronic Testing, 2017, v. 33, n. 2, p. 189, doi. 10.1007/s10836-017-5649-x
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- Publication type:
- Article
A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology.
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- Journal of Electronic Testing, 2017, v. 33, n. 4, p. 449, doi. 10.1007/s10836-017-5659-8
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- Article
A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs.
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- Journal of Electronic Testing, 2016, v. 32, n. 6, p. 749, doi. 10.1007/s10836-016-5622-0
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- Publication type:
- Article
A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets.
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- Journal of Electronic Testing, 2016, v. 32, n. 2, p. 137, doi. 10.1007/s10836-016-5573-5
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- Publication type:
- Article