Works matching DE "STATIC random access memory"
Results: 466
Impact of Temperature and Process Corners on Read Bit Line of 8T-SRAM Cell for NOR, NAND Operations.
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- IETE Journal of Research, 2025, v. 71, n. 1, p. 272, doi. 10.1080/03772063.2024.2413862
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- Article
Shallow Learning-Based Intrusion Detection System for In-Vehicle Network: ASIC Implementation.
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- Electronics (2079-9292), 2025, v. 14, n. 4, p. 683, doi. 10.3390/electronics14040683
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- Article
A data-aware write-assist 10T SRAM cell with bit-interleaving capability.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2018, v. 26, n. 5, p. 2361, doi. 10.3906/elk-1801-272
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- Article
A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications.
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- Active & Passive Electronic Components, 2023, p. 1, doi. 10.1155/2023/1697836
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- Article
Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell.
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- Active & Passive Electronic Components, 2023, p. 1, doi. 10.1155/2023/3371599
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- Article
A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node.
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- Active & Passive Electronic Components, 2023, p. 1, doi. 10.1155/2023/2364341
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- Article
DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques.
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- Active & Passive Electronic Components, 2018, p. 1, doi. 10.1155/2018/3457284
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- Article
Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells.
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- Active & Passive Electronic Components, 2018, p. 1, doi. 10.1155/2018/4512924
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- Article
SCALING THE MEMORY RELIABILITY WALL.
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- Intel Technology Journal, 2013, v. 17, n. 1, p. 18
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- Article
Low-Power 8T Memory Cell of Register File for 180 nm Technology.
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- Radioelectronics & Communications Systems, 2023, v. 66, n. 12, p. 658, doi. 10.3103/S0735272723100059
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- Article
Optimization of n-MOS 6T Nanowire SRAM Bit Cell Based on Nanowires Ratio of SiNWTs.
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- Journal of Nano- & Electronic Physics, 2020, v. 12, n. 5, p. 05020-1, doi. 10.21272/jnep.12(5).05020
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- Article
An LFSR-based address generator using optimized address partition for low power memory BIST.
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- Journal of Measurement Science & Instrumentation, 2020, n. 3, p. 205, doi. 10.3969/j.issn.1674-8042.2020.03.001
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- Article
Design of high-speed signal acquisition system and analysis of signal integrity.
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- Journal of Measurement Science & Instrumentation, 2015, v. 6, n. 1, p. 63, doi. 10.3969/j.issn.1674-8042.2015.01.012
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- Article
A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications.
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- Symmetry (20738994), 2022, v. 14, n. 4, p. N.PAG, doi. 10.3390/sym14040768
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- Article
Influence of Orbital Parameters on SEU Rate of Low-Energy Proton in Nano-SRAM Device.
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- Symmetry (20738994), 2020, v. 12, n. 12, p. 2030, doi. 10.3390/sym12122030
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- Article
Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design.
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- Journal of Nanotechnology, 2020, p. 1, doi. 10.1155/2020/7608279
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- Article
Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design.
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- Journal of Nanotechnology, 2020, p. 1, doi. 10.1155/2020/7608279
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- Article
Memory Read/Write Access Time with Loop Gain Using FinFET Based 16 Bits Array for Faster Medical Data Analysis.
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- Journal of Active & Passive Electronic Devices, 2024, v. 18, n. 2, p. 91
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- Article
Reduction of Read Power in 10T SRAM Using SVL Technique.
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- Journal of Active & Passive Electronic Devices, 2022, v. 16, n. 4, p. 339
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- Article
Performance Evolution of Different Type of 6T SRAM Cells.
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- Journal of Active & Passive Electronic Devices, 2022, v. 16, n. 4, p. 263
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- Article
Calculation of Static Noise Margin for 6T SRAM Cell.
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- Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 3/4, p. 161
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- Article
An 8T SRAM Cell with Improved I<sub>ON</sub>/I<sub>OFF</sub> Ratio and with Faster Read Speed.
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- Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 1/2, p. 127
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- Article
Low Power High Speed Gated Ground 7t Sram Using Multi-Threshold Cmos Technique.
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- Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 1/2, p. 117
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Analysis of Static Noise Margin in 6T Sram Cell At 45 And 32 NM Technology.
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- Journal of Active & Passive Electronic Devices, 2019, v. 14, n. 2/3, p. 249
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- Article
Estimation of Static Noise Margin by Butterfly Method Using Curve-Fitting Technique.
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- Journal of Active & Passive Electronic Devices, 2018, v. 13, n. 1, p. 1
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- Article
Analysis of FinFET Based 8T SRAM Cell Using Adaptive Voltage Level Techniques.
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- Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 4, p. 283
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- Article
Analysis of Different SRAM Cell Topologies and Design of 10T SRAM Cell with Improved Read Speed.
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- Journal of Active & Passive Electronic Devices, 2016, v. 11, n. 1, p. 41
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- Article
Performance Evaluation of FinFET Based 6T and Gated Ground 7T SRAM Cell's.
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- Journal of Active & Passive Electronic Devices, 2014, v. 9, n. 1, p. 1
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- Article
Modeling-Simulation of Pre-Apogee Trajectories and Stability for Low Altitude Unguided Sounding Rockets.
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- Journal of Aeronautics & Space Technologies / Havacilik ve Uzay Teknolojileri Dergisi, 2024, v. 17, p. 65
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- Article
MEMOMETER: MEMORY PUF-BASED HARDWARE METERING METHODOLOGY FOR FPGAs.
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- Electronic Device Failure Analysis, 2022, v. 24, n. 4, p. 12, doi. 10.31399/asm.edfa.2022-4.p012
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- Article
SRAM PHYSICAL FAILURE ANALYSIS CHALLENGES IN TECHNOLOGY NODES BEYOND 14 nm.
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- Electronic Device Failure Analysis, 2020, v. 22, n. 3, p. 4, doi. 10.31399/asm.edfa.2020-3.p004
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- Article
DIAGNOSTIC TECHNIQUE SELECTION FOR SRAM LOGIC TYPE FAILURES.
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- Electronic Device Failure Analysis, 2018, v. 20, n. 2, p. 18, doi. 10.31399/asm.edfa.2018-2.p018
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- Article
SOFT-ERROR SUSCEPTIBILITY OF FinFET SRAMs.
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- Electronic Device Failure Analysis, 2016, v. 18, n. 2, p. 16, doi. 10.31399/asm.edfa.2016-2.p016
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- Article
Impact of non-uniformly doped double-gate junctionless transistor on the performance of 6T-SRAM bitcell.
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- Micro & Nano Letters (Wiley-Blackwell), 2020, v. 15, n. 2, p. 72, doi. 10.1049/mnl.2019.0375
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- Article
Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM.
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- Micro & Nano Letters (Wiley-Blackwell), 2018, v. 13, n. 7, p. 965, doi. 10.1049/mnl.2017.0867
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- Article
Ternary static random access memory using quantum dot gate field-effect transistor.
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- Micro & Nano Letters (Wiley-Blackwell), 2015, v. 10, n. 11, p. 621, doi. 10.1049/mnl.2015.0200
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- Article
基于 SRAM 型 FPGA 的多源自主重构方法.
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- Systems Engineering & Electronics, 2022, v. 44, n. 4, p. 1093, doi. 10.12305/j.issn.1001506X.2022.04.04
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- Article
Low Power Full Adder Design Using PTM Transistor Model.
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- Carpathian Journal of Electrical Engineering, 2019, v. 12, n. 2, p. 15, doi. 10.2478/cjece-2019-0011
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- Article
Characterization of Novel 8T SRAM with Low Leakage and Optimized Area.
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- Carpathian Journal of Electrical Engineering, 2019, v. 12, n. 1, p. 29, doi. 10.2478/cjece-2019-0006
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- Article
高世代线 TFT-LCD 面板对盒精度的提升.
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- Chinese Journal of Liquid Crystal & Displays, 2019, v. 34, n. 2, p. 136, doi. 10.3788/YJYXS20193402.0136
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- Article
A Novel Resistive Switching Identification Method through Relaxation Characteristics for Sneak-path-constrained Selectorless RRAM application.
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- Scientific Reports, 2019, v. 9, n. 1, p. N.PAG, doi. 10.1038/s41598-019-48932-5
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- Article
A NOVEL SINGLE ENDED 3T SRAM CELL USING FINFET TECHNOLOGY FOR LOW POWER APPLICATIONS.
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- i-Manager's Journal on Electronics Engineering, 2024, v. 14, n. 4, p. 25, doi. 10.26634/jele.14.4.20911
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- Article
A NOVEL 1T-1D SINGLE ENDED SRAM CELL USING FINFET TECHNOLOGY FOR LOW POWER APPLICATIONS.
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- i-Manager's Journal on Electronics Engineering, 2024, v. 14, n. 3, p. 6, doi. 10.26634/jele.14.3.20286
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- Article
IMPLEMENTATION OF LOW POWER HIGH SPEED 64-BIT MEMORY UNIT USING 8T SRAM CELL AT 70 NM TECHNOLOGY.
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- i-Manager's Journal on Electronics Engineering, 2018, v. 8, n. 4, p. 26, doi. 10.26634/jele.8.4.14782
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- Article
DESIGN OF DUAL-POWER-SUPPLY-SRAM AND MEASURE OF ACTIVE AND STANDBY MODE POWER BY USING BL CALCULATOR.
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- i-Manager's Journal on Electronics Engineering, 2018, v. 8, n. 4, p. 19, doi. 10.26634/jele.8.4.13995
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- Article
DESIGN AND ANALYSIS OF SRAM CELL USING PULSED LATCH CIRCUIT IN DIFFERENT CMOS TECHNOLOGIES.
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- i-Manager's Journal on Electronics Engineering, 2017, v. 7, n. 4, p. 16, doi. 10.26634/jele.7.4.13685
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- Article
EFFICIENT IMPLEMENTATION OF GATE OXIDE WITH AND WITHOUT BREAKDOWN IN SRAM - BISR FOR WORD ORIENTED MEMORIES.
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- i-Manager's Journal on Electronics Engineering, 2014, v. 4, n. 3, p. 20, doi. 10.26634/jele.4.3.2677
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- Article
Power and Threshold Voltage Analysis of 14 nm FinFET 12T SRAM Cell for Low Power Applications.
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- Journal of Nano- & Electronic Physics, 2022, v. 14, n. 5, p. 1, doi. 10.21272/jnep.14(5).05008
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- Article
A genetic algorithm‐based on‐orbit self‐repair implementation for SRAM FPGAs.
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- Expert Systems, 2022, v. 39, n. 10, p. 1, doi. 10.1111/exsy.13039
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- Article
Introducing edge intelligence to smart meters via federated split learning.
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- Nature Communications, 2024, v. 15, n. 1, p. 1, doi. 10.1038/s41467-024-53352-9
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- Article