Structured ASICs head for the niches.
- Published in:
- Electronics Systems & Software, 2005, v. 3, n. 4, p. 45
- Publication type:
- Article
Works about STANDARD cells
Results: 16
1
2
The influence of yield model parameters on the probability of defect occurrence.
- Published in:
- Journal of Telecommunications & Information Technology, 2007, v. 2007, n. 3, p. 101, doi. 10.26636/jtit.2007.3.840
- By:
- Publication type:
- Article
3
VLSI Implementation of Fixed-Point Lattice Wave Digital Filters for Increased Sampling Rate.
- Published in:
- Radioengineering, 2016, v. 25, n. 4, p. 821, doi. 10.13164/re.2016.0821
- By:
- Publication type:
- Article
4
Technology news.
- Published in:
- Biofuels, Bioproducts & Biorefining, 2013, v. 7, n. 6, p. 637, doi. 10.1002/bbb.1457
- Publication type:
- Article
5
Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library.
- Published in:
- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 11, p. -1, doi. 10.1142/S0218126616501346
- By:
- Publication type:
- Article
6
A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT.
- Published in:
- Journal of Circuits, Systems & Computers, 2014, v. 23, n. 2, p. -1, doi. 10.1142/S0218126614500169
- By:
- Publication type:
- Article
7
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library.
- Published in:
- Journal of Electronic Testing, 2018, v. 34, n. 6, p. 735, doi. 10.1007/s10836-018-5760-7
- By:
- Publication type:
- Article
8
Design of Low-Power High-Performance FinFET Standard Cells.
- Published in:
- Circuits, Systems & Signal Processing, 2018, v. 37, n. 5, p. 1789, doi. 10.1007/s00034-017-0646-y
- By:
- Publication type:
- Article
9
Orthogonal polynomials non-linearity compensation for a digital VCO-based ADC.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 11, p. 915, doi. 10.1049/el.2016.0717
- By:
- Publication type:
- Article
10
Closed-Loop Supply Chains for Spent Batteries.
- Published in:
- Interfaces, 2003, v. 33, n. 6, p. 57, doi. 10.1287/inte.33.6.57.25183
- By:
- Publication type:
- Article
11
Near-Threshold Flip-Flop Standard Cell Embedded in Commercial Standard-Cell Libraries.
- Published in:
- International Review on Computers & Software, 2012, v. 7, n. 1, p. 246
- By:
- Publication type:
- Article
12
NOVEL SETUP TIME MODEL FOR STANDARD CELL LIBRARY CHARACTERIZATION.
- Published in:
- i-Manager's Journal on Circuits & Systems, 2018, v. 6, n. 3, p. 9, doi. 10.26634/jcir.6.3.14566
- By:
- Publication type:
- Article
13
Identifying transistor-level yield limiters in the FinFET era.
- Published in:
- EE: Evaluation Engineering, 2017, v. 56, n. 5, p. 18
- By:
- Publication type:
- Article
14
Active memory controller.
- Published in:
- Journal of Supercomputing, 2012, v. 62, n. 1, p. 510, doi. 10.1007/s11227-011-0735-9
- By:
- Publication type:
- Article
15
Characterizing a standard cell library for large scale design of memristive based signal processing.
- Published in:
- IET Circuits, Devices & Systems (Wiley-Blackwell), 2022, v. 16, n. 1, p. 13, doi. 10.1049/cds2.12076
- By:
- Publication type:
- Article
16
A VLSI placement method using genetic algorithm considering hierarchical structure of solution space.
- Published in:
- Electrical Engineering in Japan, 2000, v. 131, n. 1, p. 86, doi. 10.1002/(SICI)1520-6416(20000415)131:1<86::AID-EEJ9>3.0.CO;2-5
- By:
- Publication type:
- Article