Works matching DE "SILICON-on-insulator metal oxide semiconductor field-effect transistors"

Results: 12

Strain and Dimension Effects on the Threshold Voltage of Nanoscale Fully Depleted Strained-SOI TFETs.

Published in:

Advances in Condensed Matter Physics, 2015, v. 2015, p. 1, doi. 10.1155/2015/850383

By:

Li, Yu-Chen;
Zhang, He-Ming;
Liu, Shu-lin;
Hu, Hui-Yong

Publication type:

Article

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure.

Published in:

Journal of Electronic Testing, 2016, v. 32, n. 6, p. 763, doi. 10.1007/s10836-016-5625-x

By:

Liu, Jun;
Huang, Yu;
Lu, Kai

Publication type:

Article

IGBT Dynamic Loss Reduction through Device Level Soft Switching.

Published in:

Energies (19961073), 2018, v. 11, n. 5, p. 1182, doi. 10.3390/en11051182

By:

Ma, Lan;
Xu, Hongbing;
Huang, Alex Q.;
Zou, Jianxiao;
Li, Kai

Publication type:

Article

Revision of interface coupling in ultra-thin body silicon-on-insulator MOSFETs.

Published in:

Semiconductor Physics, Quantum Electronics & Optoelectronics, 2013, v. 16, n. 3, p. 300

By:

Rudenko, T.;
Nazarov, A.;
Kilchytska, V.;
Flandre, D.;
Popov, V.;
Ilnitsky, M.;
Lysenko, V.

Publication type:

Article

Empirical and Theoretical Modeling of Low-Frequency Noise Behavior of Ultrathin Silicon-on-Insulator MOSFETs Aiming at Low-Voltage and Low-Energy Regime.

Published in:

Micromachines, 2019, v. 10, n. 1, p. 5, doi. 10.3390/mi10010005

By:

Omura, Yasuhisa

Publication type:

Article

A 1.9- GHz silicon-on-insulator CMOS stacked- FET power amplifier with uniformly distributed voltage stresses.

Published in:

International Journal of Circuit Theory & Applications, 2017, v. 45, n. 11, p. 1660, doi. 10.1002/cta.2325

By:

Im, Donggu;
Kwon, Kuduck;
Lee, In‐Young

Publication type:

Article

The Search for the Integrable Qubit.

Published in:

Clefs CEA (English), 2018, n. 66, p. 36

By:

Vinet, Maud;
Sanquer, Marc;
De Franceschi, Silvano

Publication type:

Article

PERFORMANCE ANALYSIS OF MODIFIED SOURCE JUNCTIONLESS FULLY DEPLETED SILICON ON INSULATOR MOSFET.

Published in:

i-Manager's Journal on Electronics Engineering, 2017, v. 8, n. 2, p. 44

By:

CHAUHAN, MANVENDRA SINGH;
CHAUHAN, RAJEEV KUMAR

Publication type:

Article

Numerical Simulation and Mathematical Modeling of 3D DG SOI MOSFET with the Influence of Biasing with Back Gate.

Published in:

Journal of Nano- & Electronic Physics, 2017, v. 9, n. 5, p. 1, doi. 10.21272/jnep.9(5).05002

By:

Goel, Neha;
Pandey, Manoj Kumar

Publication type:

Article

Comparison of Three Dimensional Partially and Fully Depleted SOI MOSFET Characteristics Using Mathcad.

Published in:

Journal of Nano- & Electronic Physics, 2016, v. 8, n. 1, p. 1, doi. 10.21272/jnep.8(1).01041

By:

Goel, Neha;
Pandey, Manoj Kumar

Publication type:

Article

Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit.

Published in:

Journal of Low Temperature Physics, 2016, v. 184, n. 1/2, p. 217, doi. 10.1007/s10909-016-1522-z

By:

Wada, T.;
Arai, Y.;
Baba, S.;
Hanaoka, M.;
Hattori, Y.;
Ikeda, H.;
Kaneda, H.;
Kochi, C.;
Miyachi, A.;
Nagase, K.;
Nakaya, H.;
Ohno, M.;
Oyabu, S.;
Suzuki, T.;
Ukai, S.;
Watanabe, K.;
Yamamoto, K.

Publication type:

Article

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy.

Published in:

Journal of Low Temperature Physics, 2016, v. 184, n. 1/2, p. 449, doi. 10.1007/s10909-016-1551-7

By:

Nagase, Koichi;
Wada, Takehiko;
Ikeda, Hirokazu;
Arai, Yasuo;
Ohno, Morifumi;
Hanaoka, Misaki;
Kanada, Hidehiro;
Oyabu, Shinki;
Hattori, Yasuki;
Ukai, Sota;
Suzuki, Toyoaki;
Watanabe, Kentaroh;
Baba, Shunsuke;
Kochi, Chihiro;
Yamamoto, Keita

Publication type:

Article