CMOS Technology: Conventional Module Design for Faster Data Computations.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 1, p. 42, doi. 10.31838/jvcs/05.01.06
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- Publication type:
- Article
Works matching DE "SEQUENTIAL circuits"
Results: 143
1
2
Fundamental Flip-Flop Design: Comparative Analysis.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2023, v. 5, n. 1, p. 1, doi. 10.31838/jvcs/05.01.01
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- Publication type:
- Article
3
Parts-per-Billion Detection of Hydrogen Sulfide via Cavity Ring-Down Spectroscopy.
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- Photonics, 2025, v. 12, n. 3, p. 284, doi. 10.3390/photonics12030284
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- Article
4
Design of reversible sequential circuits using electro-optic effect of lithium-niobate-based Mach-Zehnder interferometers.
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- Optical Engineering, 2016, v. 55, n. 12, p. 1, doi. 10.1117/1.OE.55.12.125105
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- Article
5
OPTIMIZING THE OPERATION OF CHARGING SELFGENERATING RESONANT INVERTERS.
- Published in:
- Eastern-European Journal of Enterprise Technologies, 2022, v. 115, n. 5, p. 23, doi. 10.15587/1729-4061.2022.252148
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- Article
6
Module‐based design method using clocking scheme for quantum‐dot cellular automata.
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- International Journal of Circuit Theory & Applications, 2022, v. 50, n. 2, p. 448, doi. 10.1002/cta.3185
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- Article
7
Functional Delay Test Generation Approach Using a Software Prototype of the Circuit.
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- Computer Science & Information Systems, 2013, v. 10, n. 3, p. 1165, doi. 10.2298/CSIS120416019B
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- Article
8
The Relationship between IT Outsourcing and Business and IT Alignment: an Explorative Study.
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- Computer Science & Information Systems, 2013, v. 10, n. 3, p. 973, doi. 10.2298/CSIS120526020S
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- Publication type:
- Article
9
Design and Simulation of Multi-State D-Latch Circuit Using QDC-SWS FETs.
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- International Journal of High Speed Electronics & Systems, 2023, v. 32, n. 2-4, p. 1, doi. 10.1142/S012915642350009X
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- Article
10
Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis.
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- PLoS ONE, 2024, v. 19, n. 3, p. 1, doi. 10.1371/journal.pone.0300073
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- Article
11
Dynamic current mode logic based flip-flop design for robust and low-power security integrated circuits.
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- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 18, p. 1236, doi. 10.1049/el.2017.2415
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- Article
12
Human Activity Recognition System Based-on Sequential Logic Circuits and Statistical Models.
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- GSTF Journal on Computing, 2017, v. 5, n. 3, p. 42, doi. 10.5176/2251-3043_5.3.376
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- Article
13
ENHANCED CLOCK GATING TECHNIQUE FOR POWER OPTIMIZATION IN SRAM AND SEQUENTIAL CIRCUIT.
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- Journal of Automation, Mobile Robotics & Intelligent Systems, 2021, v. 15, n. 2, p. 32, doi. 10.14313/JAMRIS/2-2021/11
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- Article
14
ASIC and FPGA Implementation of an Adaptive Convolutional Encoder and Viterbi Decoder.
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- IETE Journal of Research, 2025, v. 71, n. 3, p. 768, doi. 10.1080/03772063.2024.2442035
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- Article
15
Design of Reversible Serial Adder Based on EPOE Expressions for Computational Applications.
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- IETE Journal of Research, 2024, v. 70, n. 9, p. 7396, doi. 10.1080/03772063.2024.2353349
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- Article
16
Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design.
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- IETE Journal of Research, 2024, v. 70, n. 5, p. 5176, doi. 10.1080/03772063.2023.2228747
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- Article
17
Design of CNTFET-based Ternary Ring and Up–Down Counter Cells.
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- IETE Journal of Research, 2024, v. 70, n. 5, p. 5149, doi. 10.1080/03772063.2023.2225469
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- Article
18
A Novel Double-Gate MOSFET Architecture as an Inverter.
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- IETE Journal of Research, 2023, v. 69, n. 11, p. 8218, doi. 10.1080/03772063.2022.2048712
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- Article
19
Circuit Level Implementation for Insulated Shallow Extension Silicon on Nothing (ISE-SON) MOSFET: A Novel Device Architecture.
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- IETE Journal of Research, 2013, v. 59, n. 4, p. 404, doi. 10.4103/0377-2063.118053
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- Article
20
System-on-chips Design Using ISCAS Benchmark Circuits - An Approach to Fault Injection and Simulation Based on Verilog HDL.
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- IETE Journal of Research, 2012, v. 58, n. 2, p. 107, doi. 10.4103/0377-2063.96177
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- Publication type:
- Article
21
Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors.
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- IETE Journal of Research, 2012, v. 58, n. 1, p. 24, doi. 10.4103/0377-2063.94078
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- Article
22
Analytical Computation of the Area of Pinched Hysteresis Loops of Ideal Mem-Elements.
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- Radioengineering, 2013, v. 22, n. 1, p. 132
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- Article
23
A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test.
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- Radioengineering, 2011, v. 20, n. 2, p. 533
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- Article
24
Special Issue on Future Trends in Nanocomputing: Message of Guest Editors.
- Published in:
- Journal of Integrated Circuits & Systems, 2021, v. 16, n. 1, p. 1, doi. 10.29292/jics.v16i1.486
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- Publication type:
- Article
25
Digital Circuits and Systems based on Single-Electron Tunneling Technology.
- Published in:
- Journal of Integrated Circuits & Systems, 2021, v. 16, n. 1, p. 1, doi. 10.29292/jics.v16i1.475
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- Publication type:
- Article
26
Efficient techniques for fault detection and location of multiple controlled Toffoli-based reversible circuit.
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- Quantum Information Processing, 2021, v. 20, n. 11, p. 1, doi. 10.1007/s11128-021-03292-w
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- Article
27
Implementation of sequential game on quantum circuits.
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- Quantum Information Processing, 2020, v. 19, n. 4, p. 1, doi. 10.1007/s11128-020-2607-9
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- Article
28
Powering DNA strand-displacement reactions with a continuous flow reactor.
- Published in:
- Natural Computing, 2021, v. 20, n. 4, p. 821, doi. 10.1007/s11047-020-09795-2
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- Article
29
Direct synthesis for sequential networks with an arbitrary number of outputs.
- Published in:
- International Journal of RF & Microwave Computer-Aided Engineering, 2022, v. 32, n. 12, p. 1, doi. 10.1002/mmce.23537
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- Publication type:
- Article
30
First Steps in Creating Online Testable Reversible Sequential Circuits.
- Published in:
- VLSI Design, 2018, p. 1, doi. 10.1155/2018/6153274
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- Article
31
Using Multivalued Cartesian Genetic Programming (M-CGP) for Automatic Design of Digital Sequential Circuits.
- Published in:
- Applied Sciences (2076-3417), 2024, v. 14, n. 23, p. 11153, doi. 10.3390/app142311153
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- Article
32
Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures.
- Published in:
- Applied Sciences (2076-3417), 2024, v. 14, n. 19, p. 8604, doi. 10.3390/app14198604
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- Publication type:
- Article
33
Voltage-Controlled Spin-Orbit-Torque-Based Nonvolatile Flip-Flop Designs for Ultra-Low-Power Applications.
- Published in:
- Applied Sciences (2076-3417), 2023, v. 13, n. 20, p. 11316, doi. 10.3390/app132011316
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- Publication type:
- Article
34
Performance comparison of all-optical logic gates using electro-optic effect in MZI-based waveguide switch at 1.46 µm.
- Published in:
- Journal of Optical Communications, 2023, v. 44, n. 1, p. s231, doi. 10.1515/joc-2020-0125
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- Publication type:
- Article
35
Design of One-Bit Magnitude Comparator using Photonic Crystals.
- Published in:
- Journal of Optical Communications, 2019, v. 40, n. 4, p. 363, doi. 10.1515/joc-2017-0084
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- Publication type:
- Article
36
Design of Optical SR Latch and Flip-Flop Using Electro-Optic Effect Inside Lithium–Niobate-Based Mach–Zehnder Interferometers.
- Published in:
- Journal of Optical Communications, 2019, v. 40, n. 2, p. 119, doi. 10.1515/joc-2017-0053
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- Publication type:
- Article
37
All-Optical Half-Adder Circuit Based on Beam Interference Principle of Photonic Crystal.
- Published in:
- Journal of Optical Communications, 2018, v. 39, n. 1, p. 13, doi. 10.1515/joc-2016-0121
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- Publication type:
- Article
38
Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime.
- Published in:
- International Journal on Intelligent Electronics Systems, 2014, v. 8, n. 1, p. 8, doi. 10.18000/ijies.30133
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- Publication type:
- Article
39
Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems.
- Published in:
- Energies (19961073), 2022, v. 15, n. 7, p. 2636, doi. 10.3390/en15072636
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- Publication type:
- Article
40
A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks.
- Published in:
- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 6, p. 1, doi. 10.1142/S021812662450097X
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- Publication type:
- Article
41
A Novel Test Pattern Optimization Method Using Recurrent Neural Network.
- Published in:
- Journal of Circuits, Systems & Computers, 2024, v. 33, n. 4, p. 1, doi. 10.1142/S0218126624500762
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- Publication type:
- Article
42
QCA-Based Pulse/Bit Sequence Detector Using Low Quantum Cost D-Flip Flop.
- Published in:
- Journal of Circuits, Systems & Computers, 2023, v. 32, n. 5, p. 1, doi. 10.1142/S0218126623500822
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- Publication type:
- Article
43
Exploiting Energy–Quality (E–Q) Tradeoffs: A Case Study on Color-to-Grayscale Converters with Approximate Design on FPGA.
- Published in:
- Journal of Circuits, Systems & Computers, 2021, v. 30, n. 04, p. N.PAG, doi. 10.1142/S0218126621500626
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- Publication type:
- Article
44
QCA-Based RAM Design Using a Resilient Reversible Gate with Improved Performance.
- Published in:
- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 13, p. N.PAG, doi. 10.1142/S0218126620502096
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- Publication type:
- Article
45
General Method to Design Reversible Universal n-Bit Up/Down Counters.
- Published in:
- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 10, p. N.PAG, doi. 10.1142/S0218126620501650
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- Publication type:
- Article
46
Low Power Synthesis of Finite State Machines - State Assignment Decomposition Algorithm.
- Published in:
- Journal of Circuits, Systems & Computers, 2018, v. 27, n. 3, p. -1, doi. 10.1142/S021812661850041X
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- Publication type:
- Article
47
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning.
- Published in:
- Journal of Circuits, Systems & Computers, 2016, v. 25, n. 5, p. -1, doi. 10.1142/S021812661650033X
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- Publication type:
- Article
48
IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS.
- Published in:
- Journal of Circuits, Systems & Computers, 2013, v. 22, n. 5, p. -1, doi. 10.1142/S0218126613500333
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- Publication type:
- Article
49
USING SAT-BASED TECHNIQUES IN LOW POWER STATE ASSIGNMENT.
- Published in:
- Journal of Circuits, Systems & Computers, 2011, v. 20, n. 8, p. 1605, doi. 10.1142/S0218126611007980
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- Publication type:
- Article
50
SAMPLING CORRELATION SOURCES FOR TIMING YIELD ANALYSIS OF SEQUENTIAL CIRCUITS WITH CLOCK NETWORKS.
- Published in:
- Journal of Circuits, Systems & Computers, 2011, v. 20, n. 8, p. 1547, doi. 10.1142/S0218126611008043
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- Publication type:
- Article